nu MOS-based sorter for arithmetic applications

The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some arithmetic demonstrators. In particular, both an (8×8)-multiplier and a (15,4) counter which use a sorter as the main building block have been implemented. Traditional disadvantages...

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Detalles Bibliográficos
Autores: Rodríguez Villegas, Esther, Avedillo de Juan, María José, Quintana Toledo, José María, Huertas Sánchez, Gloria, Rueda Rueda, Adoración
Tipo de recurso: artículo
Estado:Versión aceptada para publicación
Fecha de publicación:2000
País:España
Institución:Universidad de Sevilla (US)
Repositorio:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/76361
Acceso en línea:https://hdl.handle.net/11441/76361
https://doi.org/10.1155/2000/57240
Access Level:acceso abierto
Palabra clave:vMOS circuits
Threshold logic
Sorter circuits
Arithmetic circuits
id ES_bcf3e6d1fcfaecb3715ee40590b7d2c9
oai_identifier_str oai:idus.us.es:11441/76361
network_acronym_str ES
network_name_str España
repository_id_str
spelling nu MOS-based sorter for arithmetic applicationsRodríguez Villegas, EstherAvedillo de Juan, María JoséQuintana Toledo, José MaríaHuertas Sánchez, GloriaRueda Rueda, AdoraciónvMOS circuitsThreshold logicSorter circuitsArithmetic circuitsThe capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some arithmetic demonstrators. In particular, both an (8×8)-multiplier and a (15,4) counter which use a sorter as the main building block have been implemented. Traditional disadvantages of binary sorters such as their hardware intensive nature are avoided by using νMOS circuits. It allows both an improving of previous results for multipliers based on a similar architecture, and to obtain a new type of counter which shows a reduced delay when compared to a conventional implementation.Comisión Interministerial de Ciencia y Tecnología TIC97-0648Hindawi Publishing CorporationElectrónica y ElectromagnetismoComisión Interministerial de Ciencia y Tecnología (CICYT). España2000info:eu-repo/semantics/articleinfo:eu-repo/semantics/acceptedVersionapplication/pdfapplication/pdfhttps://hdl.handle.net/11441/76361https://doi.org/10.1155/2000/57240reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésVLSI Design, 11 (2), 129-136.TIC97-0648http://dx.doi.org/10.1155/2000/57240info:eu-repo/semantics/openAccessoai:idus.us.es:11441/763612026-06-17T12:51:07Z
dc.title.none.fl_str_mv nu MOS-based sorter for arithmetic applications
title nu MOS-based sorter for arithmetic applications
spellingShingle nu MOS-based sorter for arithmetic applications
Rodríguez Villegas, Esther
vMOS circuits
Threshold logic
Sorter circuits
Arithmetic circuits
title_short nu MOS-based sorter for arithmetic applications
title_full nu MOS-based sorter for arithmetic applications
title_fullStr nu MOS-based sorter for arithmetic applications
title_full_unstemmed nu MOS-based sorter for arithmetic applications
title_sort nu MOS-based sorter for arithmetic applications
dc.creator.none.fl_str_mv Rodríguez Villegas, Esther
Avedillo de Juan, María José
Quintana Toledo, José María
Huertas Sánchez, Gloria
Rueda Rueda, Adoración
author Rodríguez Villegas, Esther
author_facet Rodríguez Villegas, Esther
Avedillo de Juan, María José
Quintana Toledo, José María
Huertas Sánchez, Gloria
Rueda Rueda, Adoración
author_role author
author2 Avedillo de Juan, María José
Quintana Toledo, José María
Huertas Sánchez, Gloria
Rueda Rueda, Adoración
author2_role author
author
author
author
dc.contributor.none.fl_str_mv Electrónica y Electromagnetismo
Comisión Interministerial de Ciencia y Tecnología (CICYT). España
dc.subject.none.fl_str_mv vMOS circuits
Threshold logic
Sorter circuits
Arithmetic circuits
topic vMOS circuits
Threshold logic
Sorter circuits
Arithmetic circuits
description The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some arithmetic demonstrators. In particular, both an (8×8)-multiplier and a (15,4) counter which use a sorter as the main building block have been implemented. Traditional disadvantages of binary sorters such as their hardware intensive nature are avoided by using νMOS circuits. It allows both an improving of previous results for multipliers based on a similar architecture, and to obtain a new type of counter which shows a reduced delay when compared to a conventional implementation.
publishDate 2000
dc.date.none.fl_str_mv 2000
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/acceptedVersion
format article
status_str acceptedVersion
dc.identifier.none.fl_str_mv https://hdl.handle.net/11441/76361
https://doi.org/10.1155/2000/57240
url https://hdl.handle.net/11441/76361
https://doi.org/10.1155/2000/57240
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv VLSI Design, 11 (2), 129-136.
TIC97-0648
http://dx.doi.org/10.1155/2000/57240
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv Hindawi Publishing Corporation
publisher.none.fl_str_mv Hindawi Publishing Corporation
dc.source.none.fl_str_mv reponame:idUS. Depósito de Investigación de la Universidad de Sevilla
instname:Universidad de Sevilla (US)
instname_str Universidad de Sevilla (US)
reponame_str idUS. Depósito de Investigación de la Universidad de Sevilla
collection idUS. Depósito de Investigación de la Universidad de Sevilla
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869418159091482624
score 15,301629

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