Application of a floating well concept to a latch-up-free, low-cost, smart power high-side switch technology
The aim of this brief is to present an original design methodology that permits implementing latch-up-free smart power circuits on a very simple, cost-effective technology. The basic concept used for this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up...
| Autores: | , , , , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 1993 |
| País: | España |
| Institución: | Universidad de Barcelona |
| Repositorio: | Dipòsit Digital de la UB |
| OAI Identifier: | oai:diposit.ub.edu:2445/8761 |
| Acceso en línea: | https://hdl.handle.net/2445/8761 |
| Access Level: | acceso abierto |
| Palabra clave: | Circuits integrats Circuits electrònics MOS integrated circuits Power integrated circuits Switching circuits |
| Sumario: | The aim of this brief is to present an original design methodology that permits implementing latch-up-free smart power circuits on a very simple, cost-effective technology. The basic concept used for this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up. |
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