Efficient hardware implementation of finite field arithmetic AB + C for Binary ring-LWE based post-quantum cryptography

Post-quantum cryptography (PQC) has gained significant attention from the community recently as it is proven that the existing public-key cryptosystems are vulnerable to the attacks launched from the well-developed quantum computers. The finite field arithmetic AB + C, where A and C are integer poly...

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Detalles Bibliográficos
Autores: Xie, Jiafeng, He, Pengzhou, Wang, Xiaofang, Imaña Pascual, José Luis
Tipo de recurso: artículo
Fecha de publicación:2022
País:España
Institución:Universidad Complutense de Madrid (UCM)
Repositorio:Docta Complutense
Idioma:inglés
OAI Identifier:oai:docta.ucm.es:20.500.14352/71695
Acceso en línea:https://hdl.handle.net/20.500.14352/71695
Access Level:acceso abierto
Palabra clave:004.8
Multipliers
Parallel
Binary ring-learning-with-errors
Finite field arithmetic
FPGA platform
Hardware design
Post-quantum cryptography
Inteligencia artificial (Informática)
1203.04 Inteligencia Artificial
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oai_identifier_str oai:docta.ucm.es:20.500.14352/71695
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repository_id_str
spelling Efficient hardware implementation of finite field arithmetic AB + C for Binary ring-LWE based post-quantum cryptographyXie, JiafengHe, PengzhouWang, XiaofangImaña Pascual, José Luis004.8MultipliersParallelBinary ring-learning-with-errorsFinite field arithmeticFPGA platformHardware designPost-quantum cryptographyInteligencia artificial (Informática)1203.04 Inteligencia ArtificialPost-quantum cryptography (PQC) has gained significant attention from the community recently as it is proven that the existing public-key cryptosystems are vulnerable to the attacks launched from the well-developed quantum computers. The finite field arithmetic AB + C, where A and C are integer polynomials and B is a binary polynomial, is the key component for the binary Ring-learning-with-errors (BRLWE)-based encryption scheme (a low-complexity PQC suitable for emerging lightweight applications). In this paper, we propose a novel hardware implementation of the finite field arithmetic AB + C through three stages of inter-dependent efforts: (i) a rigorous mathematical formulation process is presented first; (ii) an efficient hardware architecture is then presented with detailed description; (iii) a thorough implementation has also been given along with the comparison. Overall, (i) the proposed basic structure (u = 1) outperforms the existing designs, e.g., it involves 55.9% less area-delay product (ADP) than [13] for n = 512; (ii) the proposed design also offers very efficient performance in time-complexity and can be used in many future applications.IEEE Institute of Electrical and Electronics EngineersUniversidad Complutense de Madrid20222022-04-0120222022-04-01journal articlehttp://purl.org/coar/resource_type/c_6501info:eu-repo/semantics/articleapplication/pdfhttps://hdl.handle.net/20.500.14352/71695reponame:Docta Complutenseinstname:Universidad Complutense de Madrid (UCM)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:docta.ucm.es:20.500.14352/716952026-06-02T12:44:21Z
dc.title.none.fl_str_mv Efficient hardware implementation of finite field arithmetic AB + C for Binary ring-LWE based post-quantum cryptography
title Efficient hardware implementation of finite field arithmetic AB + C for Binary ring-LWE based post-quantum cryptography
spellingShingle Efficient hardware implementation of finite field arithmetic AB + C for Binary ring-LWE based post-quantum cryptography
Xie, Jiafeng
004.8
Multipliers
Parallel
Binary ring-learning-with-errors
Finite field arithmetic
FPGA platform
Hardware design
Post-quantum cryptography
Inteligencia artificial (Informática)
1203.04 Inteligencia Artificial
title_short Efficient hardware implementation of finite field arithmetic AB + C for Binary ring-LWE based post-quantum cryptography
title_full Efficient hardware implementation of finite field arithmetic AB + C for Binary ring-LWE based post-quantum cryptography
title_fullStr Efficient hardware implementation of finite field arithmetic AB + C for Binary ring-LWE based post-quantum cryptography
title_full_unstemmed Efficient hardware implementation of finite field arithmetic AB + C for Binary ring-LWE based post-quantum cryptography
title_sort Efficient hardware implementation of finite field arithmetic AB + C for Binary ring-LWE based post-quantum cryptography
dc.creator.none.fl_str_mv Xie, Jiafeng
He, Pengzhou
Wang, Xiaofang
Imaña Pascual, José Luis
author Xie, Jiafeng
author_facet Xie, Jiafeng
He, Pengzhou
Wang, Xiaofang
Imaña Pascual, José Luis
author_role author
author2 He, Pengzhou
Wang, Xiaofang
Imaña Pascual, José Luis
author2_role author
author
author
dc.contributor.none.fl_str_mv Universidad Complutense de Madrid
dc.subject.none.fl_str_mv 004.8
Multipliers
Parallel
Binary ring-learning-with-errors
Finite field arithmetic
FPGA platform
Hardware design
Post-quantum cryptography
Inteligencia artificial (Informática)
1203.04 Inteligencia Artificial
topic 004.8
Multipliers
Parallel
Binary ring-learning-with-errors
Finite field arithmetic
FPGA platform
Hardware design
Post-quantum cryptography
Inteligencia artificial (Informática)
1203.04 Inteligencia Artificial
description Post-quantum cryptography (PQC) has gained significant attention from the community recently as it is proven that the existing public-key cryptosystems are vulnerable to the attacks launched from the well-developed quantum computers. The finite field arithmetic AB + C, where A and C are integer polynomials and B is a binary polynomial, is the key component for the binary Ring-learning-with-errors (BRLWE)-based encryption scheme (a low-complexity PQC suitable for emerging lightweight applications). In this paper, we propose a novel hardware implementation of the finite field arithmetic AB + C through three stages of inter-dependent efforts: (i) a rigorous mathematical formulation process is presented first; (ii) an efficient hardware architecture is then presented with detailed description; (iii) a thorough implementation has also been given along with the comparison. Overall, (i) the proposed basic structure (u = 1) outperforms the existing designs, e.g., it involves 55.9% less area-delay product (ADP) than [13] for n = 512; (ii) the proposed design also offers very efficient performance in time-complexity and can be used in many future applications.
publishDate 2022
dc.date.none.fl_str_mv 2022
2022-04-01
2022
2022-04-01
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://hdl.handle.net/20.500.14352/71695
url https://hdl.handle.net/20.500.14352/71695
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv IEEE Institute of Electrical and Electronics Engineers
publisher.none.fl_str_mv IEEE Institute of Electrical and Electronics Engineers
dc.source.none.fl_str_mv reponame:Docta Complutense
instname:Universidad Complutense de Madrid (UCM)
instname_str Universidad Complutense de Madrid (UCM)
reponame_str Docta Complutense
collection Docta Complutense
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15.300719

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