Efficient hardware arithmetic for inverted binary ring-LWE based post-quantum cryptography
Ring learning-with-errors (RLWE)-based encryption scheme is a lattice-based cryptographic algorithm that constitutes one of the most promising candidates for Post-Quantum Cryptography (PQC) standardization due to its efficient implementation and low computational complexity. Binary Ring-LWE (BRLWE)...
| Autores: | , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2022 |
| País: | España |
| Institución: | Universidad Complutense de Madrid (UCM) |
| Repositorio: | Docta Complutense |
| Idioma: | inglés |
| OAI Identifier: | oai:docta.ucm.es:20.500.14352/71499 |
| Acceso en línea: | https://hdl.handle.net/20.500.14352/71499 |
| Access Level: | acceso abierto |
| Palabra clave: | 004.8 Polynomial multiplication Implementation Architecture Lightweight Computer architecture Hardware Arithmetic Cryptography Encryption Loading Elliptic curve cryptography Binary ring-LWE Hardware design Lattice-based LFSR Post-quantum cryptography Polynomial arithmetic Inteligencia artificial (Informática) 1203.04 Inteligencia Artificial |
| Sumario: | Ring learning-with-errors (RLWE)-based encryption scheme is a lattice-based cryptographic algorithm that constitutes one of the most promising candidates for Post-Quantum Cryptography (PQC) standardization due to its efficient implementation and low computational complexity. Binary Ring-LWE (BRLWE) is a new optimized variant of RLWE, which achieves smaller computational complexity and higher efficient hardware implementations. In this paper, two efficient architectures based on Linear-Feedback Shift Register (LFSR) for the arithmetic used in Inverted Binary Ring-LWE (InvBRLWE)-based encryption scheme are presented, namely the operation of A center dot B+C over the polynomial ring ${Z}_q/(x<^>n+1)$ . The first architecture optimizes the resource usage for major computation and has a novel input processing setup to speed up the overall processing latency with minimized input loading cycles. The second architecture deploys an innovative serial-in serial-out processing format to reduce the involved area usage further yet maintains a regular input loading time-complexity. Experimental results show that the architectures presented here improve the complexities obtained by competing schemes found in the literature, e.g., involving 71.23% less area-delay product than recent designs. Both architectures are highly efficient in terms of area-time complexities and can be extended for deploying in different lightweight application environments. |
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