Multicore architecture prototyping on reconfigurable devices

In the the last decades several performance walls were hit. The memory wall and the power wall are limiting the performance scaling of digital microprocessors. Homogeneous multicores rely on thread-level parallelism, which is challenging to exploit. New heterogeneous architectures promise higher per...

ver descrição completa

Detalhes bibliográficos
Autor: Arcas Abella, Oriol
Tipo de documento: tese
Estado:Versão publicada
Data de publicação:2016
País:España
Recursos:CBUC, CESCA
Repositório:TDR. Tesis Doctorales en Red
OAI Identifier:oai:www.tdx.cat:10803/393894
Acesso em linha:http://hdl.handle.net/10803/393894
https://dx.doi.org/10.5821/dissertation-2117-96324
Access Level:Acceso aberto
Palavra-chave:Àrees temàtiques de la UPC::Informàtica
004
id ES_b3eb96b24f4b5d2d52fc2f52e08fc977
oai_identifier_str oai:www.tdx.cat:10803/393894
network_acronym_str ES
network_name_str España
repository_id_str
dc.title.none.fl_str_mv Multicore architecture prototyping on reconfigurable devices
title Multicore architecture prototyping on reconfigurable devices
spellingShingle Multicore architecture prototyping on reconfigurable devices
Arcas Abella, Oriol
Àrees temàtiques de la UPC::Informàtica
004
title_short Multicore architecture prototyping on reconfigurable devices
title_full Multicore architecture prototyping on reconfigurable devices
title_fullStr Multicore architecture prototyping on reconfigurable devices
title_full_unstemmed Multicore architecture prototyping on reconfigurable devices
title_sort Multicore architecture prototyping on reconfigurable devices
dc.creator.none.fl_str_mv Arcas Abella, Oriol
author Arcas Abella, Oriol
author_facet Arcas Abella, Oriol
author_role author
dc.contributor.none.fl_str_mv Cristal Kestelman, Adrián
Ünsal, Osman
Sönmez, Nehir
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.subject.none.fl_str_mv Àrees temàtiques de la UPC::Informàtica
004
topic Àrees temàtiques de la UPC::Informàtica
004
description In the the last decades several performance walls were hit. The memory wall and the power wall are limiting the performance scaling of digital microprocessors. Homogeneous multicores rely on thread-level parallelism, which is challenging to exploit. New heterogeneous architectures promise higher performance per watt rates, but software simulators have limited capacity to research them. In this thesis we investigate the advantages of Field-Programmable Gate Array devices (FPGA) for multicore research. We developed three prototypes, implementing up to 24 cores in a single FPGA, showing their superior performance and precision compared to software simulators. Moreover, our prototypes perform full-system emulation and are totally modifiable. We use our prototypes to implement novel architectural extensions such as Transactional Memory (TM). This use case allowed us to research different needs that computer architects may have, and how to implement them on FPGAs. We developed several techniques to offer profiling, debugging and verification techniques in each stage of the design process. These solutions may bridge the gap between FPGA-based hardware design and computer architects. In particular, we place a special stress on non-obtrusive techniques, so that the precision of the emulation is not affected. Based on the current trends and the sustained growth in the high-level synthesis community, we expect FPGAs to become an integral part of computer architecture design in the next years.
publishDate 2016
dc.date.none.fl_str_mv 2016
2016
2016
dc.type.none.fl_str_mv info:eu-repo/semantics/doctoralThesis
info:eu-repo/semantics/publishedVersion
format doctoralThesis
status_str publishedVersion
dc.identifier.none.fl_str_mv http://hdl.handle.net/10803/393894
https://dx.doi.org/10.5821/dissertation-2117-96324
url http://hdl.handle.net/10803/393894
https://dx.doi.org/10.5821/dissertation-2117-96324
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.rights.none.fl_str_mv http://creativecommons.org/licenses/by-nc-sa/4.0/
info:eu-repo/semantics/openAccess
rights_invalid_str_mv http://creativecommons.org/licenses/by-nc-sa/4.0/
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 171 p.
application/pdf
application/pdf
dc.publisher.none.fl_str_mv Universitat Politècnica de Catalunya
publisher.none.fl_str_mv Universitat Politècnica de Catalunya
dc.source.none.fl_str_mv TDX (Tesis Doctorals en Xarxa)
reponame:TDR. Tesis Doctorales en Red
instname:CBUC, CESCA
instname_str CBUC, CESCA
reponame_str TDR. Tesis Doctorales en Red
collection TDR. Tesis Doctorales en Red
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869417217751252992
spelling Multicore architecture prototyping on reconfigurable devicesArcas Abella, OriolÀrees temàtiques de la UPC::Informàtica004In the the last decades several performance walls were hit. The memory wall and the power wall are limiting the performance scaling of digital microprocessors. Homogeneous multicores rely on thread-level parallelism, which is challenging to exploit. New heterogeneous architectures promise higher performance per watt rates, but software simulators have limited capacity to research them. In this thesis we investigate the advantages of Field-Programmable Gate Array devices (FPGA) for multicore research. We developed three prototypes, implementing up to 24 cores in a single FPGA, showing their superior performance and precision compared to software simulators. Moreover, our prototypes perform full-system emulation and are totally modifiable. We use our prototypes to implement novel architectural extensions such as Transactional Memory (TM). This use case allowed us to research different needs that computer architects may have, and how to implement them on FPGAs. We developed several techniques to offer profiling, debugging and verification techniques in each stage of the design process. These solutions may bridge the gap between FPGA-based hardware design and computer architects. In particular, we place a special stress on non-obtrusive techniques, so that the precision of the emulation is not affected. Based on the current trends and the sustained growth in the high-level synthesis community, we expect FPGAs to become an integral part of computer architecture design in the next years.En les darreres dècades s'ha xocat amb diversos "murs" de rendiment. El mur de la memòria i el mur de la potència estan limitant l'escalat del rendiment dels microprocessadors digitals. Els multiprocessadors homogenis depenen del paral·lelisme a nivell de fil d'execució, el qual és difícil de rendibilitzar. Les noves arquitectures heterogènies prometen més rendiment per watt, però els simuladors de software tenen una capacitat limitada per investigar-les. En aquesta tesi investiguem els avantatges de les Field-Programmable Gate Arrays (FPGA, o matrius de portes programables in situ) per a investigació sobre multiprocessadors. Hem desenvolupat tres prototipus que implementen fins a 24 nuclis en una sola FPGA, mostrant els seus rendiment i precisió superiors als dels simuladors de software. A més, els nostres prototipus realitzen emulació del sistema complet i són completament modificables. Hem utilitzat els nostres prototipus per implementar noves extensions arquitectòniques com la Transactional Memory (TM, o memòria transaccional). Aquest cas d'ús ens ha permès investigar les necessitats que els arquitectes de computadors poden tenir, i com implementar-les en una FPGA. Hem desenvolupat diverses tècniques que ofereixen traces, depuració i verificació en cada etapa del procés de disseny. Aquestes solucions poden reduir l'escletxa entre els simuladors basats en FPGA i els arquitectes de computadors. En concret, hem posar especial èmfasi en tècniques que no interfereixin amb l'execució, per tal que la precisió de la simulació no es vegi afectada. A partir de les tendències actuals i l'augment sostingut de la comunitat de síntesis d'alt nivell, preveiem que les FPGA esdevindran una part integral del disseny d'arquitectures de computadors en els propers anys.DOCTORAT EN ARQUITECTURA DE COMPUTADORS (Pla 2007)Universitat Politècnica de CatalunyaCristal Kestelman, AdriánÜnsal, OsmanSönmez, NehirUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors201620162016info:eu-repo/semantics/doctoralThesisinfo:eu-repo/semantics/publishedVersion171 p.application/pdfapplication/pdfhttp://hdl.handle.net/10803/393894https://dx.doi.org/10.5821/dissertation-2117-96324TDX (Tesis Doctorals en Xarxa)reponame:TDR. Tesis Doctorales en Redinstname:CBUC, CESCAInglésL'accés als continguts d'aquesta tesi queda condicionat a l'acceptació de les condicions d'ús establertes per la següent llicència Creative Commons: http://creativecommons.org/licenses/by-nc-sa/4.0/http://creativecommons.org/licenses/by-nc-sa/4.0/info:eu-repo/semantics/openAccessoai:www.tdx.cat:10803/3938942026-06-14T12:46:07Z
score 15,300724

Registros relacionados