Probabilistically analysable real-time systems (PROARTIS)

Critical real-time ebedded (CRTE) Systems require safe and tight worst-case execution time (WCET) estimations to provide required safety levels and keep costs low. However, CRTE Systems require increasing performance to satisfy performance needs of existing and new features. Such performance can be...

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Detalles Bibliográficos
Autor: Abella Ferrer, Jaime
Tipo de recurso: informe técnico
Fecha de publicación:2013
País:España
Institución:Varias* (Consorci de Biblioteques Universitáries de Catalunya, Centre de Serveis Científics i Acadèmics de Catalunya)
Repositorio:Recercat. Dipósit de la Recerca de Catalunya
OAI Identifier:oai:recercat.cat:2072/212759
Acceso en línea:http://hdl.handle.net/2072/212759
Access Level:acceso abierto
Palabra clave:Critical real-Time Embedded Systems (CRTES)
Worst-Case Execution Time (WCET)
Probabilistic analysis
Randomization
Processor deisgn
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spelling Probabilistically analysable real-time systems (PROARTIS)Abella Ferrer, JaimeCritical real-Time Embedded Systems (CRTES)Worst-Case Execution Time (WCET)Probabilistic analysisRandomizationProcessor deisgnCritical real-time ebedded (CRTE) Systems require safe and tight worst-case execution time (WCET) estimations to provide required safety levels and keep costs low. However, CRTE Systems require increasing performance to satisfy performance needs of existing and new features. Such performance can be only achieved by means of more agressive hardware architectures, which are much harder to analyze from a WCET perspective. The main features considered include cache memòries and multi-core processors.Thus, althoug such features provide higher performance, corrent WCET analysis methods are unable to provide tight WCET estimations. In fact, WCET estimations become worse than for simple rand less powerful hardware. The main reason is the fact that hardware behavior is deterministic but unknown and, therefore, the worst-case behavior must be assumed most of the time, leading to large WCET estimations. The purpose of this project is developing new hardware designs together with WCET analysis tools able to provide tight and safe WCET estimations. In order to do so, those pieces of hardware whose behavior is not easily analyzable due to lack of accurate information during WCET analysis will be enhanced to produce a probabilistically analyzable behavior. Thus, even if the worst-case behavior cannot be removed, its probabilty can be bounded, and hence, a safe and tight WCET can be provided for a particular safety level in line with the safety levels of the remaining components of the system. During the first year the project we have developed molt of the evaluation infraestructure as well as the techniques hardware techniques to analyze cache memories. During the second year those techniques have been evaluated, and new purely-softwar techniques have been developed.Agència de Gestió d'Ajuts Universitaris i de RecercaBarcelona Supercomputing Center2013info:eu-repo/semantics/report63 p.application/pdfhttp://hdl.handle.net/2072/212759RECERCAT (Dipòsit de la Recerca de Catalunya)reponame:Recercat. Dipósit de la Recerca de Catalunyainstname:Varias* (Consorci de Biblioteques Universitáries de Catalunya, Centre de Serveis Científics i Acadèmics de Catalunya)CatalánEls ajuts de l'AGAUR;2009BP_B00260info:eu-repo/semantics/openAccessL'accés als continguts d'aquest document queda condicionat a l'acceptació de les condicions d'ús establertes per la següent llicència Creative Commons: http://creativecommons.org/licenses/by-nc-nd/3.0/es/oai:recercat.cat:2072/2127592026-05-29T05:05:01Z
dc.title.none.fl_str_mv Probabilistically analysable real-time systems (PROARTIS)
title Probabilistically analysable real-time systems (PROARTIS)
spellingShingle Probabilistically analysable real-time systems (PROARTIS)
Abella Ferrer, Jaime
Critical real-Time Embedded Systems (CRTES)
Worst-Case Execution Time (WCET)
Probabilistic analysis
Randomization
Processor deisgn
title_short Probabilistically analysable real-time systems (PROARTIS)
title_full Probabilistically analysable real-time systems (PROARTIS)
title_fullStr Probabilistically analysable real-time systems (PROARTIS)
title_full_unstemmed Probabilistically analysable real-time systems (PROARTIS)
title_sort Probabilistically analysable real-time systems (PROARTIS)
dc.creator.none.fl_str_mv Abella Ferrer, Jaime
author Abella Ferrer, Jaime
author_facet Abella Ferrer, Jaime
author_role author
dc.contributor.none.fl_str_mv Agència de Gestió d'Ajuts Universitaris i de Recerca
Barcelona Supercomputing Center
dc.subject.none.fl_str_mv Critical real-Time Embedded Systems (CRTES)
Worst-Case Execution Time (WCET)
Probabilistic analysis
Randomization
Processor deisgn
topic Critical real-Time Embedded Systems (CRTES)
Worst-Case Execution Time (WCET)
Probabilistic analysis
Randomization
Processor deisgn
description Critical real-time ebedded (CRTE) Systems require safe and tight worst-case execution time (WCET) estimations to provide required safety levels and keep costs low. However, CRTE Systems require increasing performance to satisfy performance needs of existing and new features. Such performance can be only achieved by means of more agressive hardware architectures, which are much harder to analyze from a WCET perspective. The main features considered include cache memòries and multi-core processors.Thus, althoug such features provide higher performance, corrent WCET analysis methods are unable to provide tight WCET estimations. In fact, WCET estimations become worse than for simple rand less powerful hardware. The main reason is the fact that hardware behavior is deterministic but unknown and, therefore, the worst-case behavior must be assumed most of the time, leading to large WCET estimations. The purpose of this project is developing new hardware designs together with WCET analysis tools able to provide tight and safe WCET estimations. In order to do so, those pieces of hardware whose behavior is not easily analyzable due to lack of accurate information during WCET analysis will be enhanced to produce a probabilistically analyzable behavior. Thus, even if the worst-case behavior cannot be removed, its probabilty can be bounded, and hence, a safe and tight WCET can be provided for a particular safety level in line with the safety levels of the remaining components of the system. During the first year the project we have developed molt of the evaluation infraestructure as well as the techniques hardware techniques to analyze cache memories. During the second year those techniques have been evaluated, and new purely-softwar techniques have been developed.
publishDate 2013
dc.date.none.fl_str_mv 2013
dc.type.none.fl_str_mv info:eu-repo/semantics/report
format report
dc.identifier.none.fl_str_mv http://hdl.handle.net/2072/212759
url http://hdl.handle.net/2072/212759
dc.language.none.fl_str_mv Catalán
language_invalid_str_mv Catalán
dc.relation.none.fl_str_mv Els ajuts de l'AGAUR;2009BP_B00260
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 63 p.
application/pdf
dc.source.none.fl_str_mv RECERCAT (Dipòsit de la Recerca de Catalunya)
reponame:Recercat. Dipósit de la Recerca de Catalunya
instname:Varias* (Consorci de Biblioteques Universitáries de Catalunya, Centre de Serveis Científics i Acadèmics de Catalunya)
instname_str Varias* (Consorci de Biblioteques Universitáries de Catalunya, Centre de Serveis Científics i Acadèmics de Catalunya)
reponame_str Recercat. Dipósit de la Recerca de Catalunya
collection Recercat. Dipósit de la Recerca de Catalunya
repository.name.fl_str_mv
repository.mail.fl_str_mv
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