Implementation of an AFDX Interface with Zynq SoC Board in FPGA

This work is based on the Hardware development of the Transmission part for the communication inside the satellite. Our goal is move as much as possible of the software part into the Field-programmable gate array (FPGA) matrix due to the single event upsets (SEU). This project is part of the collabo...

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Autores: Corral González, Pablo, Molina, Fernando, De Scals Martin, GUILLERMO, Rodriguez, Alberto
Tipo de recurso: artículo
Fecha de publicación:2020
País:España
Institución:Universidad Miguel Hernández de Elche
Repositorio:REDIUMH. Depósito Digital de la UMH
OAI Identifier:oai:dspace.umh.es:11000/35076
Acceso en línea:https://hdl.handle.net/11000/35076
Access Level:acceso abierto
Palabra clave:Aerospace electronics
Aerospace simulation
AFDX
Latency measurements
CDU::6 - Ciencias aplicadas::62 - Ingeniería. Tecnología
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spelling Implementation of an AFDX Interface with Zynq SoC Board in FPGACorral González, PabloMolina, FernandoDe Scals Martin, GUILLERMORodriguez, AlbertoAerospace electronicsAerospace simulationAFDXLatency measurementsCDU::6 - Ciencias aplicadas::62 - Ingeniería. TecnologíaThis work is based on the Hardware development of the Transmission part for the communication inside the satellite. Our goal is move as much as possible of the software part into the Field-programmable gate array (FPGA) matrix due to the single event upsets (SEU). This project is part of the collaborative project called “Mission: NET@SPACE”. It was chosen by the European Commission under the Seventh Framework Program for Research (FP7) to develop an Avionics Full Duplex Switched Ethernet (AFDX) demonstrator based in FPGA. It has to be able to receive and transmit frames and enhance the robustness. The scheduling of the protocol should also be moved into the hardware, by still keeping a small footprint of the whole design. In this paper, we introduce the theory and used technologies, the project flow and development, including the decisions and milestones, to arrive at the end to the further possibilities and conclusions.Kaunas University of TechnologyDepartamentos de la UMH::Ingeniería de Comunicaciones202520252020info:eu-repo/semantics/articleapplication/pdf5application/pdfhttps://hdl.handle.net/11000/35076reponame:REDIUMH. Depósito Digital de la UMHinstname:Universidad Miguel Hernández de ElcheInglés265https://doi.org/10.5755/J01.EIE.26.5.26008info:eu-repo/semantics/openAccessAttribution-NonCommercial-NoDerivatives 4.0 Internacionalhttp://creativecommons.org/licenses/by-nc-nd/4.0/oai:dspace.umh.es:11000/350762026-05-27T13:36:21Z
dc.title.none.fl_str_mv Implementation of an AFDX Interface with Zynq SoC Board in FPGA
title Implementation of an AFDX Interface with Zynq SoC Board in FPGA
spellingShingle Implementation of an AFDX Interface with Zynq SoC Board in FPGA
Corral González, Pablo
Aerospace electronics
Aerospace simulation
AFDX
Latency measurements
CDU::6 - Ciencias aplicadas::62 - Ingeniería. Tecnología
title_short Implementation of an AFDX Interface with Zynq SoC Board in FPGA
title_full Implementation of an AFDX Interface with Zynq SoC Board in FPGA
title_fullStr Implementation of an AFDX Interface with Zynq SoC Board in FPGA
title_full_unstemmed Implementation of an AFDX Interface with Zynq SoC Board in FPGA
title_sort Implementation of an AFDX Interface with Zynq SoC Board in FPGA
dc.creator.none.fl_str_mv Corral González, Pablo
Molina, Fernando
De Scals Martin, GUILLERMO
Rodriguez, Alberto
author Corral González, Pablo
author_facet Corral González, Pablo
Molina, Fernando
De Scals Martin, GUILLERMO
Rodriguez, Alberto
author_role author
author2 Molina, Fernando
De Scals Martin, GUILLERMO
Rodriguez, Alberto
author2_role author
author
author
dc.contributor.none.fl_str_mv Departamentos de la UMH::Ingeniería de Comunicaciones
dc.subject.none.fl_str_mv Aerospace electronics
Aerospace simulation
AFDX
Latency measurements
CDU::6 - Ciencias aplicadas::62 - Ingeniería. Tecnología
topic Aerospace electronics
Aerospace simulation
AFDX
Latency measurements
CDU::6 - Ciencias aplicadas::62 - Ingeniería. Tecnología
description This work is based on the Hardware development of the Transmission part for the communication inside the satellite. Our goal is move as much as possible of the software part into the Field-programmable gate array (FPGA) matrix due to the single event upsets (SEU). This project is part of the collaborative project called “Mission: NET@SPACE”. It was chosen by the European Commission under the Seventh Framework Program for Research (FP7) to develop an Avionics Full Duplex Switched Ethernet (AFDX) demonstrator based in FPGA. It has to be able to receive and transmit frames and enhance the robustness. The scheduling of the protocol should also be moved into the hardware, by still keeping a small footprint of the whole design. In this paper, we introduce the theory and used technologies, the project flow and development, including the decisions and milestones, to arrive at the end to the further possibilities and conclusions.
publishDate 2020
dc.date.none.fl_str_mv 2020
2025
2025
dc.type.none.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://hdl.handle.net/11000/35076
url https://hdl.handle.net/11000/35076
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv 26
5
https://doi.org/10.5755/J01.EIE.26.5.26008
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
Attribution-NonCommercial-NoDerivatives 4.0 Internacional
http://creativecommons.org/licenses/by-nc-nd/4.0/
eu_rights_str_mv openAccess
rights_invalid_str_mv Attribution-NonCommercial-NoDerivatives 4.0 Internacional
http://creativecommons.org/licenses/by-nc-nd/4.0/
dc.format.none.fl_str_mv application/pdf
5
application/pdf
dc.publisher.none.fl_str_mv Kaunas University of Technology
publisher.none.fl_str_mv Kaunas University of Technology
dc.source.none.fl_str_mv reponame:REDIUMH. Depósito Digital de la UMH
instname:Universidad Miguel Hernández de Elche
instname_str Universidad Miguel Hernández de Elche
reponame_str REDIUMH. Depósito Digital de la UMH
collection REDIUMH. Depósito Digital de la UMH
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15.811543

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