Implementation of an AFDX Interface with Zynq SoC Board in FPGA
This work is based on the Hardware development of the Transmission part for the communication inside the satellite. Our goal is move as much as possible of the software part into the Field-programmable gate array (FPGA) matrix due to the single event upsets (SEU). This project is part of the collabo...
| Autores: | , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2020 |
| País: | España |
| Institución: | Universidad Miguel Hernández de Elche |
| Repositorio: | REDIUMH. Depósito Digital de la UMH |
| OAI Identifier: | oai:dspace.umh.es:11000/35076 |
| Acceso en línea: | https://hdl.handle.net/11000/35076 |
| Access Level: | acceso abierto |
| Palabra clave: | Aerospace electronics Aerospace simulation AFDX Latency measurements CDU::6 - Ciencias aplicadas::62 - Ingeniería. Tecnología |
| Sumario: | This work is based on the Hardware development of the Transmission part for the communication inside the satellite. Our goal is move as much as possible of the software part into the Field-programmable gate array (FPGA) matrix due to the single event upsets (SEU). This project is part of the collaborative project called “Mission: NET@SPACE”. It was chosen by the European Commission under the Seventh Framework Program for Research (FP7) to develop an Avionics Full Duplex Switched Ethernet (AFDX) demonstrator based in FPGA. It has to be able to receive and transmit frames and enhance the robustness. The scheduling of the protocol should also be moved into the hardware, by still keeping a small footprint of the whole design. In this paper, we introduce the theory and used technologies, the project flow and development, including the decisions and milestones, to arrive at the end to the further possibilities and conclusions. |
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