Efficient low-latency multiplication architecture for NIST Trinomials with RISC-V integration

Binary extension field arithmetic is widely used in several important applications such as error-correcting codes, cryptography and digital signal processing. Multiplication is usually considered the most important finite field arithmetic operation. Therefore efficient hardware architectures for mul...

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Detalles Bibliográficos
Autores: Imaña Pascual, José Luis, Piñuel Moreno, Luis, Kuo, Yao-Ming, Ruano Ramos, Óscar, García Herrero, Francisco Miguel
Tipo de recurso: artículo
Fecha de publicación:2024
País:España
Institución:Universidad Complutense de Madrid (UCM)
Repositorio:Docta Complutense
Idioma:inglés
OAI Identifier:oai:docta.ucm.es:20.500.14352/109186
Acceso en línea:https://hdl.handle.net/20.500.14352/109186
Access Level:acceso abierto
Palabra clave:004
004.056.55
Error-correcting codes
Cryptography
Finite field arithmetic
Multiplication
NIST trinomials
RISC-V
Hardware
3304 Tecnología de Los Ordenadores
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oai_identifier_str oai:docta.ucm.es:20.500.14352/109186
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repository_id_str
spelling Efficient low-latency multiplication architecture for NIST Trinomials with RISC-V integrationImaña Pascual, José LuisPiñuel Moreno, LuisKuo, Yao-MingRuano Ramos, ÓscarGarcía Herrero, Francisco Miguel004004.056.55Error-correcting codesCryptographyFinite field arithmeticMultiplicationNIST trinomialsRISC-VHardware3304 Tecnología de Los OrdenadoresBinary extension field arithmetic is widely used in several important applications such as error-correcting codes, cryptography and digital signal processing. Multiplication is usually considered the most important finite field arithmetic operation. Therefore efficient hardware architectures for multiplication are highly desired. In this brief, a new architecture for multiplication over finite fields generated by irreducible trinomials f(x) = xm + xt + 1 is presented. The architecture here proposed is based on the use of a polynomial multiplier and a cyclic shift register that can perform the multiplication in t − 1 clock cycles. The general architecture is applied to the trinomials recommended by NIST (National Institute of Standards and Technology). Furthermore, a RISC-V instruction set for the proposed multiplier is implemented and validated using VeeR-EL2 on a Nexys A7 FPGA. To the best knowledge of the authors, this is the first work that integrates the multiplication based on NIST trinomials into a RISC-V SoC. Results show an improvement of several orders of magnitude in terms of latency at a cost of less than 50% more of area.IEEEUniversidad Complutense de Madrid20242024-08-0120242024-08-01journal articlehttp://purl.org/coar/resource_type/c_6501VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/articleapplication/pdfhttps://hdl.handle.net/20.500.14352/109186reponame:Docta Complutenseinstname:Universidad Complutense de Madrid (UCM)InglésengMinisterio de Economía y Competitividad http://dx.doi.org/10.13039/501100003329 Not available PID2021-123041OB-I00open accesshttp://purl.org/coar/access_right/c_abf2Attribution 4.0 Internationalhttp://creativecommons.org/licenses/by/4.0/info:eu-repo/semantics/openAccessoai:docta.ucm.es:20.500.14352/1091862026-06-02T12:44:21Z
dc.title.none.fl_str_mv Efficient low-latency multiplication architecture for NIST Trinomials with RISC-V integration
title Efficient low-latency multiplication architecture for NIST Trinomials with RISC-V integration
spellingShingle Efficient low-latency multiplication architecture for NIST Trinomials with RISC-V integration
Imaña Pascual, José Luis
004
004.056.55
Error-correcting codes
Cryptography
Finite field arithmetic
Multiplication
NIST trinomials
RISC-V
Hardware
3304 Tecnología de Los Ordenadores
title_short Efficient low-latency multiplication architecture for NIST Trinomials with RISC-V integration
title_full Efficient low-latency multiplication architecture for NIST Trinomials with RISC-V integration
title_fullStr Efficient low-latency multiplication architecture for NIST Trinomials with RISC-V integration
title_full_unstemmed Efficient low-latency multiplication architecture for NIST Trinomials with RISC-V integration
title_sort Efficient low-latency multiplication architecture for NIST Trinomials with RISC-V integration
dc.creator.none.fl_str_mv Imaña Pascual, José Luis
Piñuel Moreno, Luis
Kuo, Yao-Ming
Ruano Ramos, Óscar
García Herrero, Francisco Miguel
author Imaña Pascual, José Luis
author_facet Imaña Pascual, José Luis
Piñuel Moreno, Luis
Kuo, Yao-Ming
Ruano Ramos, Óscar
García Herrero, Francisco Miguel
author_role author
author2 Piñuel Moreno, Luis
Kuo, Yao-Ming
Ruano Ramos, Óscar
García Herrero, Francisco Miguel
author2_role author
author
author
author
dc.contributor.none.fl_str_mv Universidad Complutense de Madrid
dc.subject.none.fl_str_mv 004
004.056.55
Error-correcting codes
Cryptography
Finite field arithmetic
Multiplication
NIST trinomials
RISC-V
Hardware
3304 Tecnología de Los Ordenadores
topic 004
004.056.55
Error-correcting codes
Cryptography
Finite field arithmetic
Multiplication
NIST trinomials
RISC-V
Hardware
3304 Tecnología de Los Ordenadores
description Binary extension field arithmetic is widely used in several important applications such as error-correcting codes, cryptography and digital signal processing. Multiplication is usually considered the most important finite field arithmetic operation. Therefore efficient hardware architectures for multiplication are highly desired. In this brief, a new architecture for multiplication over finite fields generated by irreducible trinomials f(x) = xm + xt + 1 is presented. The architecture here proposed is based on the use of a polynomial multiplier and a cyclic shift register that can perform the multiplication in t − 1 clock cycles. The general architecture is applied to the trinomials recommended by NIST (National Institute of Standards and Technology). Furthermore, a RISC-V instruction set for the proposed multiplier is implemented and validated using VeeR-EL2 on a Nexys A7 FPGA. To the best knowledge of the authors, this is the first work that integrates the multiplication based on NIST trinomials into a RISC-V SoC. Results show an improvement of several orders of magnitude in terms of latency at a cost of less than 50% more of area.
publishDate 2024
dc.date.none.fl_str_mv 2024
2024-08-01
2024
2024-08-01
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://hdl.handle.net/20.500.14352/109186
url https://hdl.handle.net/20.500.14352/109186
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.relation.none.fl_str_mv Ministerio de Economía y Competitividad http://dx.doi.org/10.13039/501100003329 Not available PID2021-123041OB-I00
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
Attribution 4.0 International
http://creativecommons.org/licenses/by/4.0/
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
Attribution 4.0 International
http://creativecommons.org/licenses/by/4.0/
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv IEEE
publisher.none.fl_str_mv IEEE
dc.source.none.fl_str_mv reponame:Docta Complutense
instname:Universidad Complutense de Madrid (UCM)
instname_str Universidad Complutense de Madrid (UCM)
reponame_str Docta Complutense
collection Docta Complutense
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,812429

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