Cita APA

Imaña Pascual, J. L., Piñuel Moreno, L., Kuo, Y., Ruano Ramos, Ó., & García Herrero, F. M. (2024). Efficient low-latency multiplication architecture for NIST Trinomials with RISC-V integration.

Citación estilo Chicago

Imaña Pascual, José Luis, Luis Piñuel Moreno, Yao-Ming Kuo, Óscar Ruano Ramos, y Francisco Miguel García Herrero. Efficient Low-latency Multiplication Architecture for NIST Trinomials With RISC-V Integration. 2024.

Cita MLA

Imaña Pascual, José Luis, et al. Efficient Low-latency Multiplication Architecture for NIST Trinomials With RISC-V Integration. 2024.