OpenPiton4HPC: optimizing OpenPiton towards high performance manycores
In recent years, numerous multicore RISC-V platforms have emerged. Development frameworks such as OpenPiton are employed in designs that aim to scale to a large number of cores. While OpenPiton presents a large flexibility, supporting different requirements and processing cores, some of its design d...
| Authors: | , , , , , , , , |
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| Format: | article |
| Publication Date: | 2024 |
| Country: | España |
| Institution: | Universitat Politècnica de Catalunya (UPC) |
| Repository: | UPCommons. Portal del coneixement obert de la UPC |
| Language: | English |
| OAI Identifier: | oai:upcommons.upc.edu:2117/423062 |
| Online Access: | https://hdl.handle.net/2117/423062 https://dx.doi.org/10.1109/JETCAS.2024.3428929 |
| Access Level: | Open access |
| Keyword: | Many-core Network-on-chip Optimization OpenPiton RISC-V Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Summary: | In recent years, numerous multicore RISC-V platforms have emerged. Development frameworks such as OpenPiton are employed in designs that aim to scale to a large number of cores. While OpenPiton presents a large flexibility, supporting different requirements and processing cores, some of its design decisions result in designs that are not optimized for High-Performance Computing (HPC) requirements. This work presents OpenPiton4HPC, an extension and optimization of OpenPiton for high-performance manycores. The key contributions are enabling multiple memory controllers, supporting router bypassing and NoC concentration, adding support for configurable cache sizes and cache block sizes, and allowing configurable bus widths in the NoC and in the cache SRAMs. On a 64-core manycore architecture, these new features and optimizations provide a geometric mean speedup of 7.2x compared to the OpenPiton baseline. |
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