Integrating the Tensor Marshaling Unit for sparse tensor algebra with a RISC-V processor
This thesis presents the first RTL implementation and integration of a Tensor Marshaling Unit (TMU) in a System on Chip, targeting the acceleration of sparse tensor operations. Sparse tensor algebra has become fundamental in domains such as machine learning, graph analytics, and computational biolog...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2025 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/452568 |
| Acceso en línea: | https://hdl.handle.net/2117/452568 |
| Access Level: | acceso abierto |
| Palabra clave: | RISC microprocessors Tensor algebra Tensor Marshaling Unit Sparse tensor operations Hardware accelerators Data-flow architectures RISC-V System on chip OpenPiton Microprocessadors RISC Àlgebra tensorial Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Sumario: | This thesis presents the first RTL implementation and integration of a Tensor Marshaling Unit (TMU) in a System on Chip, targeting the acceleration of sparse tensor operations. Sparse tensor algebra has become fundamental in domains such as machine learning, graph analytics, and computational biology, but traditional computer architectures struggle with the irregular memory access patterns and data-dependent control flow inherent to sparse workloads. The TMU addresses these limitations by decoupling tensor traversal and merging operations from computation, enabling parallel execution with the host processor. This work presents four key contributions: (1) the first RTL implementation of a TMU, capable of executing the Sparse Matrix-Vector Multiplication (SpMV) Coordinate (COO) kernel, (2) the integration of the TMU into an OpenPiton-based SoC with the CVA6 RISC-V core, (3) the development of software optimization techniques, including batching strategies and queue optimizations, and (4) a comprehensive characterization of the system, revealing important insights into the TMU’s trade-offs. The current implementation of the four contributions enabled a 1.5× average speedup and 1.9× maximum speedup with respect to a system without TMU. The obtained results demonstrated the feasibility of the TMU in a real SoC and established the first milestone of a larger effort towards implementing and integrating a more complex multi-layer, multilane TMU into an HPC-oriented many-core system. |
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