Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation
Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most critical features of the synchronization protocols in hardware and the synchronization algorithms in software. In this paper, a new clock discipline algorithm for hardware implementati...
| Authors: | , , , , |
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| Format: | article |
| Status: | Versión aceptada para publicación |
| Publication Date: | 2011 |
| Country: | España |
| Institution: | Universidad de Sevilla (US) |
| Repository: | idUS. Depósito de Investigación de la Universidad de Sevilla |
| OAI Identifier: | oai:idus.us.es:11441/52740 |
| Online Access: | http://hdl.handle.net/11441/52740 https://doi.org/10.1109/TIM.2011.2164828 |
| Access Level: | Open access |
| Keyword: | Field-programmable gate array hardware timestamping Network Time Protocol (NTP) Precision Time Protocol (PTP) synchronization system |
| Summary: | Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most critical features of the synchronization protocols in hardware and the synchronization algorithms in software. In this paper, a new clock discipline algorithm for hardware implementation is presented, allowing for full hardware implementation of synchronization systems. Measurements on field-programmable gate array prototypes show a fast convergence time (below 10 s) and a high accuracy (1 μs) for typical configuration parameters. |
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