Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation

Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most critical features of the synchronization protocols in hardware and the synchronization algorithms in software. In this paper, a new clock discipline algorithm for hardware implementati...

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Detalles Bibliográficos
Autores: Viejo Cortés, Julián, Juan Chico, Jorge, Bellido Díaz, Manuel Jesús, Millán Calderón, Alejandro, Ruiz de Clavijo Vázquez, Paulino
Tipo de recurso: artículo
Estado:Versión aceptada para publicación
Fecha de publicación:2011
País:España
Institución:Universidad de Sevilla (US)
Repositorio:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/52740
Acceso en línea:http://hdl.handle.net/11441/52740
https://doi.org/10.1109/TIM.2011.2164828
Access Level:acceso abierto
Palabra clave:Field-programmable gate array
hardware timestamping
Network Time Protocol (NTP)
Precision Time Protocol (PTP)
synchronization system
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spelling Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware ImplementationViejo Cortés, JuliánJuan Chico, JorgeBellido Díaz, Manuel JesúsMillán Calderón, AlejandroRuiz de Clavijo Vázquez, PaulinoField-programmable gate arrayhardware timestampingNetwork Time Protocol (NTP)Precision Time Protocol (PTP)synchronization systemDiscrete microprocessor-based equipment is a typical synchronization system on the market which implements the most critical features of the synchronization protocols in hardware and the synchronization algorithms in software. In this paper, a new clock discipline algorithm for hardware implementation is presented, allowing for full hardware implementation of synchronization systems. Measurements on field-programmable gate array prototypes show a fast convergence time (below 10 s) and a high accuracy (1 μs) for typical configuration parameters.Ministerio de Educación y Cultura HIPER TEC2007-61802/MICIEEE Computer SocietyTecnología ElectrónicaTIC204: Investigación y Desarrollo Digital (ID2)Ministerio de Educación y Cultura (MEC). España2011info:eu-repo/semantics/articleinfo:eu-repo/semantics/acceptedVersionapplication/pdfapplication/pdfhttp://hdl.handle.net/11441/52740https://doi.org/10.1109/TIM.2011.2164828reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésIEEE Transactions on Instrumentation and Measurement, 60 (12), 3961-3963.HIPER TEC2007-61802/MIChttp://ieeexplore.ieee.org/document/6017115/info:eu-repo/semantics/openAccessoai:idus.us.es:11441/527402026-06-17T12:51:07Z
dc.title.none.fl_str_mv Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation
title Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation
spellingShingle Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation
Viejo Cortés, Julián
Field-programmable gate array
hardware timestamping
Network Time Protocol (NTP)
Precision Time Protocol (PTP)
synchronization system
title_short Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation
title_full Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation
title_fullStr Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation
title_full_unstemmed Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation
title_sort Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation
dc.creator.none.fl_str_mv Viejo Cortés, Julián
Juan Chico, Jorge
Bellido Díaz, Manuel Jesús
Millán Calderón, Alejandro
Ruiz de Clavijo Vázquez, Paulino
author Viejo Cortés, Julián
author_facet Viejo Cortés, Julián
Juan Chico, Jorge
Bellido Díaz, Manuel Jesús
Millán Calderón, Alejandro
Ruiz de Clavijo Vázquez, Paulino
author_role author
author2 Juan Chico, Jorge
Bellido Díaz, Manuel Jesús
Millán Calderón, Alejandro
Ruiz de Clavijo Vázquez, Paulino
author2_role author
author
author
author
dc.contributor.none.fl_str_mv Tecnología Electrónica
TIC204: Investigación y Desarrollo Digital (ID2)
Ministerio de Educación y Cultura (MEC). España
dc.subject.none.fl_str_mv Field-programmable gate array
hardware timestamping
Network Time Protocol (NTP)
Precision Time Protocol (PTP)
synchronization system
topic Field-programmable gate array
hardware timestamping
Network Time Protocol (NTP)
Precision Time Protocol (PTP)
synchronization system
description Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most critical features of the synchronization protocols in hardware and the synchronization algorithms in software. In this paper, a new clock discipline algorithm for hardware implementation is presented, allowing for full hardware implementation of synchronization systems. Measurements on field-programmable gate array prototypes show a fast convergence time (below 10 s) and a high accuracy (1 μs) for typical configuration parameters.
publishDate 2011
dc.date.none.fl_str_mv 2011
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/acceptedVersion
format article
status_str acceptedVersion
dc.identifier.none.fl_str_mv http://hdl.handle.net/11441/52740
https://doi.org/10.1109/TIM.2011.2164828
url http://hdl.handle.net/11441/52740
https://doi.org/10.1109/TIM.2011.2164828
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv IEEE Transactions on Instrumentation and Measurement, 60 (12), 3961-3963.
HIPER TEC2007-61802/MIC
http://ieeexplore.ieee.org/document/6017115/
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv IEEE Computer Society
publisher.none.fl_str_mv IEEE Computer Society
dc.source.none.fl_str_mv reponame:idUS. Depósito de Investigación de la Universidad de Sevilla
instname:Universidad de Sevilla (US)
instname_str Universidad de Sevilla (US)
reponame_str idUS. Depósito de Investigación de la Universidad de Sevilla
collection idUS. Depósito de Investigación de la Universidad de Sevilla
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,301603

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