Performance modeling of the sparse matrix-vector product via convolutional neural networks
[EN] Modeling the execution time of the sparse matrix-vector multiplication (SpMV) on a current CPU architecture is especially complex due to (i) irregular memory accesses; (ii) indirect memory referencing; and (iii) low arithmetic intensity. While analytical models may yield accurate estimates for...
| Autores: | , , , , |
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| Formato: | artículo |
| Fecha de publicación: | 2020 |
| País: | España |
| Recursos: | Ajuntament de Barcelona |
| Repositorio: | RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia |
| Idioma: | inglés |
| OAI Identifier: | oai:riunet.upv.es:10251/176273 |
| Acesso em linha: | https://riunet.upv.es/handle/10251/176273 |
| Access Level: | acceso abierto |
| Palavra-chave: | Sparse matrix-vector multiplication (SpMV) Performance modeling Supervised learning Convolutional neural networks (CNNs) CIENCIAS DE LA COMPUTACION E INTELIGENCIA ARTIFICIAL ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES |
| Resumo: | [EN] Modeling the execution time of the sparse matrix-vector multiplication (SpMV) on a current CPU architecture is especially complex due to (i) irregular memory accesses; (ii) indirect memory referencing; and (iii) low arithmetic intensity. While analytical models may yield accurate estimates for the total number of cache hits/misses, they often fail to predict accurately the total execution time. In this paper, we depart from the analytic approach to instead leverage convolutional neural networks (CNNs) in order to provide an effective estimation of the performance of the SpMV operation. For this purpose, we present a high-level abstraction of the sparsity pattern of the problem matrix and propose a blockwise strategy to feed the CNN models by blocks of nonzero elements. The experimental evaluation on a representative subset of the matrices from the SuiteSparse Matrix collection demonstrates the robustness of the CNN models for predicting the SpMV performance on an Intel Haswell core. Furthermore, we show how to generalize the network models to other target architectures to estimate the performance of SpMV on an ARM A57 core |
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