Optimizing sparse matrix-vector multiplication in NEC SX-Aurora vector engine
Sparse Matrix-Vector multiplication (SpMV) is an essential piece of code used in many High Performance Computing (HPC) applications. As previous literature shows, achieving efficient vectorization and performance in modern multi-core systems is nothing straightforward. It is important then to revisi...
| Autores: | , , , |
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| Tipo de recurso: | informe técnico |
| Fecha de publicación: | 2020 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/192586 |
| Acceso en línea: | https://hdl.handle.net/2117/192586 |
| Access Level: | acceso abierto |
| Palabra clave: | High performance computing Computer architecture Sparse Matrix-Vector multiplication SpMV Vectorization Multi-core systems NEC Vector Engine Superordinadors Arquitectura d'ordinadors Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Sumario: | Sparse Matrix-Vector multiplication (SpMV) is an essential piece of code used in many High Performance Computing (HPC) applications. As previous literature shows, achieving efficient vectorization and performance in modern multi-core systems is nothing straightforward. It is important then to revisit the current stateof-the-art matrix formats and optimizations to be able to deliver deliver high performance in long vector architectures. In this tech-report, we describe how to develop an efficient implementation that achieves high throughput in the NEC Vector Engine: a 256 element-long vector architecture. Combining several pre-processing and kernel optimizations we obtain an average 12% improvement over a base SELLC-s implementation on a heterogeneous set of 24 matrices. |
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