Integration and evaluation of Triton with OmpSs-2 and RISC-V CPUs
The increasing complexity of AI workloads has amplified the demand for efficient, high-performance computing solutions. While GPUs remain the primary platform for accelerating such workloads, programming these devices effectively often requires specialized knowledge of vendor-specific APIs like CUDA...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2025 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/449427 |
| Acceso en línea: | https://hdl.handle.net/2117/449427 |
| Access Level: | acceso abierto |
| Palabra clave: | RISC microprocessors Graphics processing units Artificial intelligence Paral·lelisme basat en tasques Triton RISC-V OmpSs-2 Avaluació comparativa Vectorització GPU Task-based parallelism Microprocessadors RISC Processadors gràfics Intel·ligència artificial Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Sumario: | The increasing complexity of AI workloads has amplified the demand for efficient, high-performance computing solutions. While GPUs remain the primary platform for accelerating such workloads, programming these devices effectively often requires specialized knowledge of vendor-specific APIs like CUDA and ROCm. Triton is an emerging open-source language and compiler designed to simplify GPU programming by providing a higher-level abstraction while retaining competitive performance. This work evaluates the applicability of Triton across different hardware platforms, including GPUs and CPUs, with a particular focus on task-based programming models like OmpSs-2 and emerging architectures such as RISC-V. We port key kernels from HPCCG and GPT-2 applications to Triton and assess their performance on multiple systems. Our results indicate that while Triton enables easier development and achieves respectable performance on GPUs, its CPU backend currently falls short of optimized vendor libraries and compilers. Finally, we identify specific bottlenecks related to vectorization and register management on RISC-V and suggest avenues for future improvement. |
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