Fast Hardware Implementations of Static P Systems

In this article we present a simulator of non-deterministic static P systems using Field Programmable Gate Array (FPGA) technology. Its major feature is a high performance, achieving a constant processing time for each transition. Our approach is based on representing all possible applications as wo...

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Detalles Bibliográficos
Autores: Quirós Carmona, Juan, Verlan, Sergey, Viejo Cortés, Julián, Millán Calderón, Alejandro, Bellido Díaz, Manuel Jesús
Tipo de recurso: artículo
Estado:Versión publicada
Fecha de publicación:2016
País:España
Institución:Universidad de Sevilla (US)
Repositorio:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/80849
Acceso en línea:https://hdl.handle.net/11441/80849
Access Level:acceso abierto
Palabra clave:Reconfigurable hardware
P systems
Static P systems
FPGA
Membrane computing
Parallel implementations of membrane computing
Simulator of membrane computing
Hardware implementations of membrane computing
Parallel implementations of static P systems
Simulator of static P systems
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spelling Fast Hardware Implementations of Static P SystemsQuirós Carmona, JuanVerlan, SergeyViejo Cortés, JuliánMillán Calderón, AlejandroBellido Díaz, Manuel JesúsReconfigurable hardwareP systemsStatic P systemsFPGAMembrane computingParallel implementations of membrane computingSimulator of membrane computingHardware implementations of membrane computingParallel implementations of static P systemsSimulator of static P systemsIn this article we present a simulator of non-deterministic static P systems using Field Programmable Gate Array (FPGA) technology. Its major feature is a high performance, achieving a constant processing time for each transition. Our approach is based on representing all possible applications as words of some regular context-free language. Then, using formal power series it is possible to obtain the number of possibilities and select one of them following a uniform distribution, in a fair and non-deterministic way. According to these ideas, we yield an implementation whose results show an important speed-up, with a strong independence from the size of the P system.Ministry of Science and Innovation of the Spanish Government under the project TEC2011-27936 (HIPERSYS)European Regional Development Fund (ERDF)Ministry of Education of Spain (FPU grant AP2009-3625)ANR project SynBioTICTecnología ElectrónicaTIC204: Investigación y Desarrollo Digital2016info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionapplication/pdfapplication/pdfhttps://hdl.handle.net/11441/80849reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésComputing and Informatics, 35 (3), 687-718.TEC2011-27936AP2009-3625http://www.cai.sk/ojs/index.php/cai/article/viewArticle/1665info:eu-repo/semantics/openAccessoai:idus.us.es:11441/808492026-06-17T12:51:07Z
dc.title.none.fl_str_mv Fast Hardware Implementations of Static P Systems
title Fast Hardware Implementations of Static P Systems
spellingShingle Fast Hardware Implementations of Static P Systems
Quirós Carmona, Juan
Reconfigurable hardware
P systems
Static P systems
FPGA
Membrane computing
Parallel implementations of membrane computing
Simulator of membrane computing
Hardware implementations of membrane computing
Parallel implementations of static P systems
Simulator of static P systems
title_short Fast Hardware Implementations of Static P Systems
title_full Fast Hardware Implementations of Static P Systems
title_fullStr Fast Hardware Implementations of Static P Systems
title_full_unstemmed Fast Hardware Implementations of Static P Systems
title_sort Fast Hardware Implementations of Static P Systems
dc.creator.none.fl_str_mv Quirós Carmona, Juan
Verlan, Sergey
Viejo Cortés, Julián
Millán Calderón, Alejandro
Bellido Díaz, Manuel Jesús
author Quirós Carmona, Juan
author_facet Quirós Carmona, Juan
Verlan, Sergey
Viejo Cortés, Julián
Millán Calderón, Alejandro
Bellido Díaz, Manuel Jesús
author_role author
author2 Verlan, Sergey
Viejo Cortés, Julián
Millán Calderón, Alejandro
Bellido Díaz, Manuel Jesús
author2_role author
author
author
author
dc.contributor.none.fl_str_mv Tecnología Electrónica
TIC204: Investigación y Desarrollo Digital
dc.subject.none.fl_str_mv Reconfigurable hardware
P systems
Static P systems
FPGA
Membrane computing
Parallel implementations of membrane computing
Simulator of membrane computing
Hardware implementations of membrane computing
Parallel implementations of static P systems
Simulator of static P systems
topic Reconfigurable hardware
P systems
Static P systems
FPGA
Membrane computing
Parallel implementations of membrane computing
Simulator of membrane computing
Hardware implementations of membrane computing
Parallel implementations of static P systems
Simulator of static P systems
description In this article we present a simulator of non-deterministic static P systems using Field Programmable Gate Array (FPGA) technology. Its major feature is a high performance, achieving a constant processing time for each transition. Our approach is based on representing all possible applications as words of some regular context-free language. Then, using formal power series it is possible to obtain the number of possibilities and select one of them following a uniform distribution, in a fair and non-deterministic way. According to these ideas, we yield an implementation whose results show an important speed-up, with a strong independence from the size of the P system.
publishDate 2016
dc.date.none.fl_str_mv 2016
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv https://hdl.handle.net/11441/80849
url https://hdl.handle.net/11441/80849
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv Computing and Informatics, 35 (3), 687-718.
TEC2011-27936
AP2009-3625
http://www.cai.sk/ojs/index.php/cai/article/viewArticle/1665
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.source.none.fl_str_mv reponame:idUS. Depósito de Investigación de la Universidad de Sevilla
instname:Universidad de Sevilla (US)
instname_str Universidad de Sevilla (US)
reponame_str idUS. Depósito de Investigación de la Universidad de Sevilla
collection idUS. Depósito de Investigación de la Universidad de Sevilla
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,301603

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