Fast Hardware Implementations of Static P Systems
In this article we present a simulator of non-deterministic static P systems using Field Programmable Gate Array (FPGA) technology. Its major feature is a high performance, achieving a constant processing time for each transition. Our approach is based on representing all possible applications as wo...
| Autores: | , , , , |
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| Formato: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2016 |
| País: | España |
| Recursos: | Universidad de Sevilla (US) |
| Repositorio: | idUS. Depósito de Investigación de la Universidad de Sevilla |
| OAI Identifier: | oai:idus.us.es:11441/80849 |
| Acesso em linha: | https://hdl.handle.net/11441/80849 |
| Access Level: | acceso abierto |
| Palavra-chave: | Reconfigurable hardware P systems Static P systems FPGA Membrane computing Parallel implementations of membrane computing Simulator of membrane computing Hardware implementations of membrane computing Parallel implementations of static P systems Simulator of static P systems |
| Resumo: | In this article we present a simulator of non-deterministic static P systems using Field Programmable Gate Array (FPGA) technology. Its major feature is a high performance, achieving a constant processing time for each transition. Our approach is based on representing all possible applications as words of some regular context-free language. Then, using formal power series it is possible to obtain the number of possibilities and select one of them following a uniform distribution, in a fair and non-deterministic way. According to these ideas, we yield an implementation whose results show an important speed-up, with a strong independence from the size of the P system. |
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