Explaining dynamic cache partitioning speed ups

Cache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, these new policies present different behaviors depending on the applications th...

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Detalhes bibliográficos
Autores: Moretó Planas, Miquel|||0000-0002-9848-8758, Cazorla, Francisco, Ramírez Bellido, Alejandro, Valero Cortés, Mateo|||0000-0003-2917-2482
Formato: artículo
Fecha de publicación:2007
País:España
Recursos:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/102823
Acesso em linha:https://hdl.handle.net/2117/102823
https://dx.doi.org/10.1109/L-CA.2007.3
Access Level:acceso abierto
Palavra-chave:Microprocessors
Cache memory
Microprocessor chips
Cache storage
Microprocessadors
Memòria cau
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
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spelling Explaining dynamic cache partitioning speed upsMoretó Planas, Miquel|||0000-0002-9848-8758Cazorla, FranciscoRamírez Bellido, AlejandroValero Cortés, Mateo|||0000-0003-2917-2482MicroprocessorsCache memoryMicroprocessor chipsCache storageMicroprocessadorsMemòria cauÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadorsCache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, these new policies present different behaviors depending on the applications that are running in the architecture. In this paper, we introduce some metrics that characterize applications and allow us to give a clear and simple model to explain final throughput speed ups.Peer Reviewed20072007-01-0120172017-03-23journal articlehttp://purl.org/coar/resource_type/c_6501VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/articleapplication/pdfhttps://hdl.handle.net/2117/102823https://dx.doi.org/10.1109/L-CA.2007.3reponame:UPCommons. Portal del coneixement obert de la UPCinstname:Universitat Politècnica de Catalunya (UPC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:upcommons.upc.edu:2117/1028232026-05-27T15:37:01Z
dc.title.none.fl_str_mv Explaining dynamic cache partitioning speed ups
title Explaining dynamic cache partitioning speed ups
spellingShingle Explaining dynamic cache partitioning speed ups
Moretó Planas, Miquel|||0000-0002-9848-8758
Microprocessors
Cache memory
Microprocessor chips
Cache storage
Microprocessadors
Memòria cau
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
title_short Explaining dynamic cache partitioning speed ups
title_full Explaining dynamic cache partitioning speed ups
title_fullStr Explaining dynamic cache partitioning speed ups
title_full_unstemmed Explaining dynamic cache partitioning speed ups
title_sort Explaining dynamic cache partitioning speed ups
dc.creator.none.fl_str_mv Moretó Planas, Miquel|||0000-0002-9848-8758
Cazorla, Francisco
Ramírez Bellido, Alejandro
Valero Cortés, Mateo|||0000-0003-2917-2482
author Moretó Planas, Miquel|||0000-0002-9848-8758
author_facet Moretó Planas, Miquel|||0000-0002-9848-8758
Cazorla, Francisco
Ramírez Bellido, Alejandro
Valero Cortés, Mateo|||0000-0003-2917-2482
author_role author
author2 Cazorla, Francisco
Ramírez Bellido, Alejandro
Valero Cortés, Mateo|||0000-0003-2917-2482
author2_role author
author
author
dc.subject.none.fl_str_mv Microprocessors
Cache memory
Microprocessor chips
Cache storage
Microprocessadors
Memòria cau
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
topic Microprocessors
Cache memory
Microprocessor chips
Cache storage
Microprocessadors
Memòria cau
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
description Cache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, these new policies present different behaviors depending on the applications that are running in the architecture. In this paper, we introduce some metrics that characterize applications and allow us to give a clear and simple model to explain final throughput speed ups.
publishDate 2007
dc.date.none.fl_str_mv 2007
2007-01-01
2017
2017-03-23
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://hdl.handle.net/2117/102823
https://dx.doi.org/10.1109/L-CA.2007.3
url https://hdl.handle.net/2117/102823
https://dx.doi.org/10.1109/L-CA.2007.3
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:UPCommons. Portal del coneixement obert de la UPC
instname:Universitat Politècnica de Catalunya (UPC)
instname_str Universitat Politècnica de Catalunya (UPC)
reponame_str UPCommons. Portal del coneixement obert de la UPC
collection UPCommons. Portal del coneixement obert de la UPC
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,300719

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