Low-delay FPGA-based implementation of finite field multipliers
Arithmetic operations over binary extension fields GF(2^m) have many important applications in domains such as cryptography, code theory and digital signal processing. These applications must be fast, so low-delay implementations of arithmetic circuits are required. Among GF(2^m) arithmetic operatio...
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2021 |
| País: | España |
| Institución: | Universidad Complutense de Madrid (UCM) |
| Repositorio: | Docta Complutense |
| Idioma: | inglés |
| OAI Identifier: | oai:docta.ucm.es:20.500.14352/4479 |
| Acceso en línea: | https://hdl.handle.net/20.500.14352/4479 |
| Access Level: | acceso abierto |
| Palabra clave: | 004.8 Parallel Complexity Multipliers Bit-parallel Galois fields Polynomial basis Trinomials Inteligencia artificial (Informática) 1203.04 Inteligencia Artificial |
| Sumario: | Arithmetic operations over binary extension fields GF(2^m) have many important applications in domains such as cryptography, code theory and digital signal processing. These applications must be fast, so low-delay implementations of arithmetic circuits are required. Among GF(2^m) arithmetic operations, field multiplication is considered the most important one. For hardware implementation of multiplication over binary finite fields, irreducible trinomials and pentanomials are normally used. In this brief, low-delay FPGA-based implementations of bit-parallel GF(2^m) polynomial basis multipliers are presented, where a new multiplier based on irreducible trinomials is given. Several post-place and route implementation results in Xilinx Artix-7 FPGA for different GF(2^m) finite fields are reported. Experimental results show that the proposed multiplier exhibits the best delay, with a delay improvement of up to 4.7%, and the second best Area x Time complexities when compared with similar multipliers found in the literature. |
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