Accelerating SpMV on HBM-equipped FPGAs: hardware-software co-design and collaboration
(English) SpMV is a key linear algebra kernel at the core of many algorithms across multiple knowledge domains. Its memory-bound nature and its low arithmetic intensity make its efficient implementation a challenging problem. Usual mechanisms present in general-purpose microprocessors, such as cache...
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| Tipo de recurso: | tesis doctoral |
| Fecha de publicación: | 2025 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/449855 |
| Acceso en línea: | https://hdl.handle.net/2117/449855 https://dx.doi.org/10.5821/dissertation-2117-449855 |
| Access Level: | acceso abierto |
| Palabra clave: | FPGA SpMV HBM HLS FP64 FP32 double-precision single-precision High-performance computing Sparse matrix representation Computer architecture Iterative methods Linear algebra 004 - Informàtica Àrees temàtiques de la UPC::Informàtica |
| Sumario: | (English) SpMV is a key linear algebra kernel at the core of many algorithms across multiple knowledge domains. Its memory-bound nature and its low arithmetic intensity make its efficient implementation a challenging problem. Usual mechanisms present in general-purpose microprocessors, such as cache memories, become useless without further data transformation as the size of the problem grows beyond the capacity of the cache. The capability of FPGAs to generate application-specific logic and memory hierarchies results in performant and energy-efficient designs. This has made them an interesting alternative when trying to efficiently implement SpMV. The push by vendors to position them as HPC accelerators and the inclusion of HBM in the last generations of boards have increased this trend. Most SpMV implementations for FPGAs allow to work exclusively using single-precision floating-point arithmetic, while in the context of HPC applications, double-precision floating-point arithmetic is usually required. CSR or slightly modified versions of it are usually used as the basis for these implementations. This limits inter and intra-row parallelism due to conflicts in memory accesses, requiring the implementation to include complex logic such as arbitration or stall/retry mechanisms or to use replicated memories, increasing resource usage and limiting the scalability of the designs. This thesis presents two proposals to leverage the features offered by FPGAs, especially HBM and customizable memory hierarchies, to further improve the achieved performance and, in the case of the second proposal, allowing for a precision-agnostic design that can be synthesized to work with different arithmetic types as required. The first proposal consists of a double-precision FPGA co-designed SpMV accelerator and matrix representation. Instead of using CSR as the basis, the representation and the accelerator are defined considering all the advanced features that FPGAs offer, in a co-design approach. This approach allows maximization of inter-row and intra-row parallelism by allowing simultaneous processing of several matrix values per cycle in a fully pipelined fashion without requiring complex logic or memory replication. The proposed matrix representation allows the easy partitioning of work among different accelerators and the efficient use of HBM bandwidth. The evaluation shows that the proposed implementation outperforms state-of-the-art implementations in terms of absolute, bandwidth-relative, and energy-relative performance. The second proposal builds on the first one, increasing its arithmetic efficiency. It does so in different ways. In the first place, it improves the efficiency of the proposed encoding by reducing the amount of metadata required to process the matrix. In the second place, it increases the useful data ratio of the transformed representation by considering new hierarchical abstractions within the matrix. In the third place, it repurposes zero-padding, when present, to act as a carrier of useful data. This proposal is highly parametrizable, including the possibility of using it to generate designs working with different data types without requiring more changes than setting the desired data type at compile time. The evaluation shows that this proposal significantly improves over the first one in double-precision arithmetic. Single-precision results demonstrate its capability to improve the performance offered by state-of-the-art designs that use much higher bandwidth. |
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