Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches

[EN] Cache memories dissipate an important amount of the energy budget in current microprocessors. This is mainly due to cache cells are typically implemented with six transistors. To tackle this design concern, recent research has focused on the proposal of new cache cells. An n-bit cache cell, nam...

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Autores: Valero Bresó, Alejandro, Duato Marín, José Francisco, Sahuquillo Borrás, Julio|||0000-0001-8630-4846, Lorente Garcés, Vicente Jesús, Petit Martí, Salvador Vicente|||0000-0003-2426-4134, López Rodríguez, Pedro Juan|||0000-0003-4544-955X
Tipo de recurso: artículo
Fecha de publicación:2012
País:España
Institución:Universitat Politècnica de València (UPV)
Repositorio:RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
Idioma:inglés
OAI Identifier:oai:riunet.upv.es:10251/34853
Acceso en línea:https://riunet.upv.es/handle/10251/34853
Access Level:acceso abierto
Palabra clave:Edram memory cells
Edram capacitance
Energy consumption
Retention time
Sram memory cells
ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES
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spelling Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data cachesValero Bresó, AlejandroDuato Marín, José FranciscoSahuquillo Borrás, Julio|||0000-0001-8630-4846Lorente Garcés, Vicente JesúsPetit Martí, Salvador Vicente|||0000-0003-2426-4134López Rodríguez, Pedro Juan|||0000-0003-4544-955XEdram memory cellsEdram capacitanceEnergy consumptionRetention timeSram memory cellsARQUITECTURA Y TECNOLOGIA DE COMPUTADORES[EN] Cache memories dissipate an important amount of the energy budget in current microprocessors. This is mainly due to cache cells are typically implemented with six transistors. To tackle this design concern, recent research has focused on the proposal of new cache cells. An n-bit cache cell, namely macrocell, has been proposed in a previous work. This cell combines SRAM and eDRAM technologies with the aim of reducing energy consumption while maintaining the performance. The capacitance of eDRAM cells impacts on energy consumption and performance since these cells lose their state once the retention time expires. On such a case, data must be fetched from a lower level of the memory hierarchy, so negatively impacting on performance and energy consumption. As opposite, if the capacitance is too high, energy would be wasted without bringing performance benefits. This paper identifies the optimal capacitance for a given processor frequency. To this end, the tradeoff between performance and energy consumption of a macrocell-based cache has been evaluated varying the capacitance and frequency. Experimental results show that, compared to a conventional cache, performance losses are lower than 2% and energy savings are up to 55% for a cache with 10 fF capacitors and frequencies higher than 1 GHz. In addition, using trench capacitors, a 4-bit macrocell reduces by 29% the area of four conventional SRAM cells.This work was supported in part by Spanish CICYT under Grant TIN2009-14475-C04-01, by Consolider-Ingenio 2010 under Grant CSD2006-00046, and by European community’s Seventh Framework Programme (FP7/2007-2013) under Grant 289154.Institute of Electrical and Electronics Engineers (IEEE)Departamento de Informática de Sistemas y ComputadoresEscuela Técnica Superior de Ingeniería InformáticaGrupo de Arquitecturas ParalelasEuropean CommissionMinisterio de Ciencia e InnovaciónMinisterio de Educación y CienciaRepositorio Institucional de la Universitat Politècnica de València Riunet20122012-06-01journal articlehttp://purl.org/coar/resource_type/c_6501VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/articleapplication/pdfapplication/pdfhttps://riunet.upv.es/handle/10251/34853reponame:RiuNet. Repositorio Institucional de la Universitat Politécnica de Valénciainstname:Universitat Politècnica de València (UPV)InglésengMinisterio de Ciencia e Innovación http://dx.doi.org/10.13039/501100004837 TIN2009-14475-C04-01 Arquitecturas De Servidores, Aplicaciones Y ServiciosMinisterio de Educación y Ciencia https://doi.org/10.13039/501100008743 CSD2006-00046 Arquitecturas fiables y de altas prestaciones para centros de proceso de datos y servidores de InternetEuropean Commission https://doi.org/10.13039/501100000780 FP7 289154open accesshttp://purl.org/coar/access_right/c_abf2Reserva de todos los derechoshttp://rightsstatements.org/vocab/InC/1.0/info:eu-repo/semantics/openAccessoai:riunet.upv.es:10251/348532026-06-13T07:49:27Z
dc.title.none.fl_str_mv Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches
title Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches
spellingShingle Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches
Valero Bresó, Alejandro
Edram memory cells
Edram capacitance
Energy consumption
Retention time
Sram memory cells
ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES
title_short Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches
title_full Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches
title_fullStr Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches
title_full_unstemmed Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches
title_sort Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches
dc.creator.none.fl_str_mv Valero Bresó, Alejandro
Duato Marín, José Francisco
Sahuquillo Borrás, Julio|||0000-0001-8630-4846
Lorente Garcés, Vicente Jesús
Petit Martí, Salvador Vicente|||0000-0003-2426-4134
López Rodríguez, Pedro Juan|||0000-0003-4544-955X
author Valero Bresó, Alejandro
author_facet Valero Bresó, Alejandro
Duato Marín, José Francisco
Sahuquillo Borrás, Julio|||0000-0001-8630-4846
Lorente Garcés, Vicente Jesús
Petit Martí, Salvador Vicente|||0000-0003-2426-4134
López Rodríguez, Pedro Juan|||0000-0003-4544-955X
author_role author
author2 Duato Marín, José Francisco
Sahuquillo Borrás, Julio|||0000-0001-8630-4846
Lorente Garcés, Vicente Jesús
Petit Martí, Salvador Vicente|||0000-0003-2426-4134
López Rodríguez, Pedro Juan|||0000-0003-4544-955X
author2_role author
author
author
author
author
dc.contributor.none.fl_str_mv Departamento de Informática de Sistemas y Computadores
Escuela Técnica Superior de Ingeniería Informática
Grupo de Arquitecturas Paralelas
European Commission
Ministerio de Ciencia e Innovación
Ministerio de Educación y Ciencia
Repositorio Institucional de la Universitat Politècnica de València Riunet
dc.subject.none.fl_str_mv Edram memory cells
Edram capacitance
Energy consumption
Retention time
Sram memory cells
ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES
topic Edram memory cells
Edram capacitance
Energy consumption
Retention time
Sram memory cells
ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES
description [EN] Cache memories dissipate an important amount of the energy budget in current microprocessors. This is mainly due to cache cells are typically implemented with six transistors. To tackle this design concern, recent research has focused on the proposal of new cache cells. An n-bit cache cell, namely macrocell, has been proposed in a previous work. This cell combines SRAM and eDRAM technologies with the aim of reducing energy consumption while maintaining the performance. The capacitance of eDRAM cells impacts on energy consumption and performance since these cells lose their state once the retention time expires. On such a case, data must be fetched from a lower level of the memory hierarchy, so negatively impacting on performance and energy consumption. As opposite, if the capacitance is too high, energy would be wasted without bringing performance benefits. This paper identifies the optimal capacitance for a given processor frequency. To this end, the tradeoff between performance and energy consumption of a macrocell-based cache has been evaluated varying the capacitance and frequency. Experimental results show that, compared to a conventional cache, performance losses are lower than 2% and energy savings are up to 55% for a cache with 10 fF capacitors and frequencies higher than 1 GHz. In addition, using trench capacitors, a 4-bit macrocell reduces by 29% the area of four conventional SRAM cells.
publishDate 2012
dc.date.none.fl_str_mv 2012
2012-06-01
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://riunet.upv.es/handle/10251/34853
url https://riunet.upv.es/handle/10251/34853
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.relation.none.fl_str_mv Ministerio de Ciencia e Innovación http://dx.doi.org/10.13039/501100004837 TIN2009-14475-C04-01 Arquitecturas De Servidores, Aplicaciones Y Servicios
Ministerio de Educación y Ciencia https://doi.org/10.13039/501100008743 CSD2006-00046 Arquitecturas fiables y de altas prestaciones para centros de proceso de datos y servidores de Internet
European Commission https://doi.org/10.13039/501100000780 FP7 289154
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
Reserva de todos los derechos
http://rightsstatements.org/vocab/InC/1.0/
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
Reserva de todos los derechos
http://rightsstatements.org/vocab/InC/1.0/
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers (IEEE)
publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers (IEEE)
dc.source.none.fl_str_mv reponame:RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
instname:Universitat Politècnica de València (UPV)
instname_str Universitat Politècnica de València (UPV)
reponame_str RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
collection RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15.301603

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