Multi-operand decimal addition by efficient reuse of a binary carry-save adder tree

We present a novel method for hardware design of combined binary/decimal multi-operand adders. More specifically, we apply this method to architectures based on binary CSA (carry-save adder) trees, which are of interest for VLSI implementation of high performance multipliers and other low latency ar...

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Bibliographic Details
Authors: Vázquez Álvarez, Álvaro, Antelo Suárez, Elisardo
Format: book part
Publication Date:2010
Country:España
Institution:Universidad de Santiago de Compostela (USC)
Repository:Minerva. Repositorio Institucional de la Universidad de Santiago de Compostela
Language:English
OAI Identifier:oai:minerva.usc.gal:10347/46227
Online Access:https://hdl.handle.net/10347/46227
Access Level:Open access
Keyword:330406 Arquitectura de ordenadores
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spelling Multi-operand decimal addition by efficient reuse of a binary carry-save adder treeVázquez Álvarez, ÁlvaroAntelo Suárez, Elisardo330406 Arquitectura de ordenadoresWe present a novel method for hardware design of combined binary/decimal multi-operand adders. More specifically, we apply this method to architectures based on binary CSA (carry-save adder) trees, which are of interest for VLSI implementation of high performance multipliers and other low latency arithmetic units. A remarkable feature of the proposed method is that it allows the reuse of any binary CSA for computing the sum of BCD operands. Decimal corrections are performed in parallel, separately from the computation of the binary sum, such that the layout of the binary carry-save adder does not require any further rearrangement. As a result, the latency of the binary operation is unaffected by the incorporation of hardware support for decimal, while the latency for the decimal mode is close to the latency figures of dedicated decimal multi-operand adders. We show that our combined architecture is competitive in terms of area and delay with respect to other representative proposals, and that it has a more regular layout when implemented in a submicron VLSI technology.IEEEUniversidade de Santiago de Compostela. Departamento de Electrónica e Computación20102010-11-0120102010-11-01book parthttp://purl.org/coar/resource_type/c_3248AMhttp://purl.org/coar/version/c_ab4af688f83e57aainfo:eu-repo/semantics/bookPartapplication/pdfhttps://hdl.handle.net/10347/46227reponame:Minerva. Repositorio Institucional de la Universidad de Santiago de Compostelainstname:Universidad de Santiago de Compostela (USC)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2info:eu-repo/semantics/openAccessoai:minerva.usc.gal:10347/462272026-06-15T12:47:27Z
dc.title.none.fl_str_mv Multi-operand decimal addition by efficient reuse of a binary carry-save adder tree
title Multi-operand decimal addition by efficient reuse of a binary carry-save adder tree
spellingShingle Multi-operand decimal addition by efficient reuse of a binary carry-save adder tree
Vázquez Álvarez, Álvaro
330406 Arquitectura de ordenadores
title_short Multi-operand decimal addition by efficient reuse of a binary carry-save adder tree
title_full Multi-operand decimal addition by efficient reuse of a binary carry-save adder tree
title_fullStr Multi-operand decimal addition by efficient reuse of a binary carry-save adder tree
title_full_unstemmed Multi-operand decimal addition by efficient reuse of a binary carry-save adder tree
title_sort Multi-operand decimal addition by efficient reuse of a binary carry-save adder tree
dc.creator.none.fl_str_mv Vázquez Álvarez, Álvaro
Antelo Suárez, Elisardo
author Vázquez Álvarez, Álvaro
author_facet Vázquez Álvarez, Álvaro
Antelo Suárez, Elisardo
author_role author
author2 Antelo Suárez, Elisardo
author2_role author
dc.contributor.none.fl_str_mv Universidade de Santiago de Compostela. Departamento de Electrónica e Computación
dc.subject.none.fl_str_mv 330406 Arquitectura de ordenadores
topic 330406 Arquitectura de ordenadores
description We present a novel method for hardware design of combined binary/decimal multi-operand adders. More specifically, we apply this method to architectures based on binary CSA (carry-save adder) trees, which are of interest for VLSI implementation of high performance multipliers and other low latency arithmetic units. A remarkable feature of the proposed method is that it allows the reuse of any binary CSA for computing the sum of BCD operands. Decimal corrections are performed in parallel, separately from the computation of the binary sum, such that the layout of the binary carry-save adder does not require any further rearrangement. As a result, the latency of the binary operation is unaffected by the incorporation of hardware support for decimal, while the latency for the decimal mode is close to the latency figures of dedicated decimal multi-operand adders. We show that our combined architecture is competitive in terms of area and delay with respect to other representative proposals, and that it has a more regular layout when implemented in a submicron VLSI technology.
publishDate 2010
dc.date.none.fl_str_mv 2010
2010-11-01
2010
2010-11-01
dc.type.none.fl_str_mv book part
http://purl.org/coar/resource_type/c_3248
AM
http://purl.org/coar/version/c_ab4af688f83e57aa
dc.type.openaire.fl_str_mv info:eu-repo/semantics/bookPart
format bookPart
dc.identifier.none.fl_str_mv https://hdl.handle.net/10347/46227
url https://hdl.handle.net/10347/46227
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv IEEE
publisher.none.fl_str_mv IEEE
dc.source.none.fl_str_mv reponame:Minerva. Repositorio Institucional de la Universidad de Santiago de Compostela
instname:Universidad de Santiago de Compostela (USC)
instname_str Universidad de Santiago de Compostela (USC)
reponame_str Minerva. Repositorio Institucional de la Universidad de Santiago de Compostela
collection Minerva. Repositorio Institucional de la Universidad de Santiago de Compostela
repository.name.fl_str_mv
repository.mail.fl_str_mv
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