Design of two-stage class AB CMOS buffers: a systematic approach

A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requiremen...

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Autores: López Martín, Antonio, Algueta Algueta, José María, Acosta Cabanillas, Lucía, Ramírez Angulo, Jaime, González Carvajal, Ramón
Tipo de recurso: artículo
Fecha de publicación:2011
País:España
Institución:Universidad de Sevilla (US)
Repositorio:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/23355
Acceso en línea:http://hdl.handle.net/11441/23355
https://doi.org/10.4218/etrij.11.0110.0465
Access Level:acceso abierto
Palabra clave:Analog integrated circuits
CMOS buffer
CMOS voltage follower
Quasi-floating gate
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spelling Design of two-stage class AB CMOS buffers: a systematic approachLópez Martín, AntonioAlgueta Algueta, José MaríaAcosta Cabanillas, LucíaRamírez Angulo, JaimeGonzález Carvajal, RamónAnalog integrated circuitsCMOS bufferCMOS voltage followerQuasi-floating gateA systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 μm CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 μW).Ingeniería Electrónica2011info:eu-repo/semantics/articleapplication/pdfapplication/pdfhttp://hdl.handle.net/11441/23355https://doi.org/10.4218/etrij.11.0110.0465reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésETRI Journal, 33(3), 393-40010.4218/etrij.11.0110.0465http://dx.doi.org/10.4218/etrij.11.0110.0465info:eu-repo/semantics/openAccessoai:idus.us.es:11441/233552026-06-17T12:51:07Z
dc.title.none.fl_str_mv Design of two-stage class AB CMOS buffers: a systematic approach
title Design of two-stage class AB CMOS buffers: a systematic approach
spellingShingle Design of two-stage class AB CMOS buffers: a systematic approach
López Martín, Antonio
Analog integrated circuits
CMOS buffer
CMOS voltage follower
Quasi-floating gate
title_short Design of two-stage class AB CMOS buffers: a systematic approach
title_full Design of two-stage class AB CMOS buffers: a systematic approach
title_fullStr Design of two-stage class AB CMOS buffers: a systematic approach
title_full_unstemmed Design of two-stage class AB CMOS buffers: a systematic approach
title_sort Design of two-stage class AB CMOS buffers: a systematic approach
dc.creator.none.fl_str_mv López Martín, Antonio
Algueta Algueta, José María
Acosta Cabanillas, Lucía
Ramírez Angulo, Jaime
González Carvajal, Ramón
author López Martín, Antonio
author_facet López Martín, Antonio
Algueta Algueta, José María
Acosta Cabanillas, Lucía
Ramírez Angulo, Jaime
González Carvajal, Ramón
author_role author
author2 Algueta Algueta, José María
Acosta Cabanillas, Lucía
Ramírez Angulo, Jaime
González Carvajal, Ramón
author2_role author
author
author
author
dc.contributor.none.fl_str_mv Ingeniería Electrónica
dc.subject.none.fl_str_mv Analog integrated circuits
CMOS buffer
CMOS voltage follower
Quasi-floating gate
topic Analog integrated circuits
CMOS buffer
CMOS voltage follower
Quasi-floating gate
description A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 μm CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 μW).
publishDate 2011
dc.date.none.fl_str_mv 2011
dc.type.none.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv http://hdl.handle.net/11441/23355
https://doi.org/10.4218/etrij.11.0110.0465
url http://hdl.handle.net/11441/23355
https://doi.org/10.4218/etrij.11.0110.0465
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv ETRI Journal, 33(3), 393-400
10.4218/etrij.11.0110.0465
http://dx.doi.org/10.4218/etrij.11.0110.0465
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.source.none.fl_str_mv reponame:idUS. Depósito de Investigación de la Universidad de Sevilla
instname:Universidad de Sevilla (US)
instname_str Universidad de Sevilla (US)
reponame_str idUS. Depósito de Investigación de la Universidad de Sevilla
collection idUS. Depósito de Investigación de la Universidad de Sevilla
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,300724

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