Design of two-stage class AB CMOS buffers: a systematic approach
A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requiremen...
| Autores: | , , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2011 |
| País: | España |
| Institución: | Universidad de Sevilla (US) |
| Repositorio: | idUS. Depósito de Investigación de la Universidad de Sevilla |
| OAI Identifier: | oai:idus.us.es:11441/23355 |
| Acceso en línea: | http://hdl.handle.net/11441/23355 https://doi.org/10.4218/etrij.11.0110.0465 |
| Access Level: | acceso abierto |
| Palabra clave: | Analog integrated circuits CMOS buffer CMOS voltage follower Quasi-floating gate |
| Sumario: | A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 μm CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 μW). |
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