Power-optimal mapping of CNN applications to cloud-based Multi-FPGA platforms
Multi-FPGA platforms like Amazon Web Services F1 are perfect to accelerate multi-kernel pipelined applications, like Convolutional Neural Networks (CNNs). To reduce energy consumption, we propose to upload at runtime the best power-optimized CNN implementation for a given throughput constraint. Our...
| Autores: | , , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2020 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/340450 |
| Acceso en línea: | https://hdl.handle.net/2117/340450 https://dx.doi.org/10.1109/TCSII.2020.2998284 |
| Access Level: | acceso abierto |
| Palabra clave: | Neural networks (Computer science) Logic design Field programmable gate arrays CNN Multi-FPGA Power optimization Xarxes neuronals (Informàtica) Estructura lògica Matrius de portes programables per l'usuari Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| Sumario: | Multi-FPGA platforms like Amazon Web Services F1 are perfect to accelerate multi-kernel pipelined applications, like Convolutional Neural Networks (CNNs). To reduce energy consumption, we propose to upload at runtime the best power-optimized CNN implementation for a given throughput constraint. Our design method gives the best number of parallel instances of each kernel, their allocation to the FPGAs, the number of powered-on FPGAs and their clock frequency. This is obtained by solving a mixed-integer, non-linear optimization problem that models power and performance of each component, as well as the duration of the computation phases-data transfer between a host CPU and the FPGA memory (typically DDR), data transfer between DDR and FPGA, and FPGA computation. The results show that the power saved compared to simply clock gating the fastest implementation is obviously very high, but it is also much more significant than simply scaling the frequency of the fastest implementation or replicating the slowest implementation on multiple FPGAs. |
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