Novel Planar and Waveguide Implementations of Impedance Matching Networks Based on Tapered Lines Using Generalized Superellipses
[EN] For the practical implementation of RF and microwave impedance matching networks, a widely employed solution¿alternative to the use of classical impedance transformers¿is based on tapered lines. This paper shows a simple method to design smooth tapers that take into account the dispersion of th...
| Autores: | , , , |
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| Tipo de documento: | artigo |
| Data de publicação: | 2018 |
| País: | España |
| Recursos: | Universitat Politècnica de València (UPV) |
| Repositório: | RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia |
| Idioma: | inglês |
| OAI Identifier: | oai:riunet.upv.es:10251/120674 |
| Acesso em linha: | https://riunet.upv.es/handle/10251/120674 |
| Access Level: | Acceso aberto |
| Palavra-chave: | Impedance Dispersion Microwave circuits Planar waveguides Bandwidth Mathematical model Impedance matching Nonuniform transmission lines Planar circuits Waveguides TECNOLOGIA ELECTRONICA TEORIA DE LA SEÑAL Y COMUNICACIONES |
| Resumo: | [EN] For the practical implementation of RF and microwave impedance matching networks, a widely employed solution¿alternative to the use of classical impedance transformers¿is based on tapered lines. This paper shows a simple method to design smooth tapers that take into account the dispersion of the line and the required design bandwidth simultaneously. A planar taper has been designed in microstrip technology with the same length of classical ones but improving their performances. A waveguide prototype has also been designed with similar performance to a commercial one but with one third of its length. Both tapered structures have been obtained through the optimization of very few parameters using the same design strategy. As a result, the reflection coefficient of the tapers can be optimally adapted to a given specific mask using the prescribed value of physical length. Experimental results for both tapers are included for the validation of the proposed topologies and the related design method. |
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