FPGA implementation of an AD-HOC RISC-V system-on-chip for industrial IoT

Node devices for IoT1 need to be energy efficient and cost effective, but they do not require a high computing power in a large number of scenarios. This changes substantially in an Industrial IoT environment, where massive sensor utilization and a fast pace of events require more processing power....

Descripción completa

Detalles Bibliográficos
Autor: León González, Daniel
Tipo de recurso: tesis de maestría
Fecha de publicación:2020
País:España
Institución:Universidad Complutense de Madrid (UCM)
Repositorio:Docta Complutense
Idioma:inglés
OAI Identifier:oai:docta.ucm.es:20.500.14352/9043
Acceso en línea:https://hdl.handle.net/20.500.14352/9043
Access Level:acceso abierto
Palabra clave:004(043.3)
RISC-V
System on Chip
SoC
Zephyr
IoT
Internet of Things
FPGA
Artix 7
IIoT .
Sistema embebido
Internet de las cosas
Artix-7
IIoT.
Informática (Informática)
1203.17 Informática
id ES_5dd4d672b7bd6284ef6007d48201ffb8
oai_identifier_str oai:docta.ucm.es:20.500.14352/9043
network_acronym_str ES
network_name_str España
repository_id_str
spelling FPGA implementation of an AD-HOC RISC-V system-on-chip for industrial IoTImplementación FPGA de un SoC basado en RISC-V para IoT industrialLeón González, Daniel004(043.3)RISC-VSystem on ChipSoCZephyrIoTInternet of ThingsFPGAArtix 7IIoT .Sistema embebidoInternet de las cosasArtix-7IIoT.Informática (Informática)1203.17 InformáticaNode devices for IoT1 need to be energy efficient and cost effective, but they do not require a high computing power in a large number of scenarios. This changes substantially in an Industrial IoT environment, where massive sensor utilization and a fast pace of events require more processing power. A custom developed node, using an efficient processor and a high performance and feature-full operating system, may balance these requirements and offer an optimal solution. This project addresses the hardware implementation, using an Artix-7 FPGA2, of a prototype IIoT3 node based on the RISC-V processor architecture. The project presents the implemented custom SoC4 and the development of the necessary Zephyr OS drivers to support a proof-of-concept application, which is deployed in a star network around a custom border router. End-toend messages can be sent and received between the node and the ThingSpeak cloud platform. This document includes an analysis of the existing RISC-V processor implementations, a description of the required elements and a detailed guide of environment configuration and steps to build the complete project.Chaver Martínez, Daniel ÁngelPiñuel Moreno, LuisUniversidad Complutense de Madrid20202020-01-0120202020-01-01master thesishttp://purl.org/coar/resource_type/c_bdccinfo:eu-repo/semantics/masterThesisapplication/pdfhttps://hdl.handle.net/20.500.14352/9043reponame:Docta Complutenseinstname:Universidad Complutense de Madrid (UCM)Inglésengopen accesshttp://purl.org/coar/access_right/c_abf2Atribución-NoComercial 3.0 Españahttps://creativecommons.org/licenses/by-nc/3.0/es/info:eu-repo/semantics/openAccessoai:docta.ucm.es:20.500.14352/90432026-06-02T12:44:21Z
dc.title.none.fl_str_mv FPGA implementation of an AD-HOC RISC-V system-on-chip for industrial IoT
Implementación FPGA de un SoC basado en RISC-V para IoT industrial
title FPGA implementation of an AD-HOC RISC-V system-on-chip for industrial IoT
spellingShingle FPGA implementation of an AD-HOC RISC-V system-on-chip for industrial IoT
León González, Daniel
004(043.3)
RISC-V
System on Chip
SoC
Zephyr
IoT
Internet of Things
FPGA
Artix 7
IIoT .
Sistema embebido
Internet de las cosas
Artix-7
IIoT.
Informática (Informática)
1203.17 Informática
title_short FPGA implementation of an AD-HOC RISC-V system-on-chip for industrial IoT
title_full FPGA implementation of an AD-HOC RISC-V system-on-chip for industrial IoT
title_fullStr FPGA implementation of an AD-HOC RISC-V system-on-chip for industrial IoT
title_full_unstemmed FPGA implementation of an AD-HOC RISC-V system-on-chip for industrial IoT
title_sort FPGA implementation of an AD-HOC RISC-V system-on-chip for industrial IoT
dc.creator.none.fl_str_mv León González, Daniel
author León González, Daniel
author_facet León González, Daniel
author_role author
dc.contributor.none.fl_str_mv Chaver Martínez, Daniel Ángel
Piñuel Moreno, Luis
Universidad Complutense de Madrid
dc.subject.none.fl_str_mv 004(043.3)
RISC-V
System on Chip
SoC
Zephyr
IoT
Internet of Things
FPGA
Artix 7
IIoT .
Sistema embebido
Internet de las cosas
Artix-7
IIoT.
Informática (Informática)
1203.17 Informática
topic 004(043.3)
RISC-V
System on Chip
SoC
Zephyr
IoT
Internet of Things
FPGA
Artix 7
IIoT .
Sistema embebido
Internet de las cosas
Artix-7
IIoT.
Informática (Informática)
1203.17 Informática
description Node devices for IoT1 need to be energy efficient and cost effective, but they do not require a high computing power in a large number of scenarios. This changes substantially in an Industrial IoT environment, where massive sensor utilization and a fast pace of events require more processing power. A custom developed node, using an efficient processor and a high performance and feature-full operating system, may balance these requirements and offer an optimal solution. This project addresses the hardware implementation, using an Artix-7 FPGA2, of a prototype IIoT3 node based on the RISC-V processor architecture. The project presents the implemented custom SoC4 and the development of the necessary Zephyr OS drivers to support a proof-of-concept application, which is deployed in a star network around a custom border router. End-toend messages can be sent and received between the node and the ThingSpeak cloud platform. This document includes an analysis of the existing RISC-V processor implementations, a description of the required elements and a detailed guide of environment configuration and steps to build the complete project.
publishDate 2020
dc.date.none.fl_str_mv 2020
2020-01-01
2020
2020-01-01
dc.type.none.fl_str_mv master thesis
http://purl.org/coar/resource_type/c_bdcc
dc.type.openaire.fl_str_mv info:eu-repo/semantics/masterThesis
format masterThesis
dc.identifier.none.fl_str_mv https://hdl.handle.net/20.500.14352/9043
url https://hdl.handle.net/20.500.14352/9043
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
Atribución-NoComercial 3.0 España
https://creativecommons.org/licenses/by-nc/3.0/es/
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
Atribución-NoComercial 3.0 España
https://creativecommons.org/licenses/by-nc/3.0/es/
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:Docta Complutense
instname:Universidad Complutense de Madrid (UCM)
instname_str Universidad Complutense de Madrid (UCM)
reponame_str Docta Complutense
collection Docta Complutense
repository.name.fl_str_mv
repository.mail.fl_str_mv
_version_ 1869409057479065600
score 15,300719

Similares en LA Referencia