Efficient Hybrid Continuous-Time/Discrete-Time Cascade Modulators for Wideband Applications
This paper analyses the use of hybrid continuous-time/discrete-time cascade ΣΔ modulators for the implementation of power-efficient analog-to-digital converters in broadband wireless communication systems. Two alternative implementations of multi-rate cascade architectures are studied and compared w...
| Autores: | , |
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| Tipo de recurso: | artículo |
| Estado: | Versión enviada para evaluación y publicación |
| Fecha de publicación: | 2014 |
| País: | España |
| Institución: | Universidad de Sevilla (US) |
| Repositorio: | idUS. Depósito de Investigación de la Universidad de Sevilla |
| OAI Identifier: | oai:idus.us.es:11441/74633 |
| Acceso en línea: | https://hdl.handle.net/11441/74633 https://doi.org/10.1016/j.mejo.2013.10.017 |
| Access Level: | acceso abierto |
| Palabra clave: | Analog-to-digital converters Sigma-delta modulators Hybrid continuous-time/discrete-time Multi-rate signal processing |
| Sumario: | This paper analyses the use of hybrid continuous-time/discrete-time cascade ΣΔ modulators for the implementation of power-efficient analog-to-digital converters in broadband wireless communication systems. Two alternative implementations of multi-rate cascade architectures are studied and compared with conventional single-rate continuous-time topologies, taking into account the impact of main circuit-level error mechanisms, namely: mismatch, finite dc gain and gain-bandwidth product. In all cases, closed-form design equations are derived for the nonideal in-band noise power of all ΣΔ modulators under study, providing analytical relationships between their system-level performance and the corresponding circuit-level error parameters. Theoretical predictions match simulation results, showing that the lowest performance degradation is obtained by a new kind of multi-rate hybrid ΣΔ modulator, in which the front-end (continuous-time) stage operates at a higher rate than the back-end (discrete-time) stages. As a case study, the design of a hybrid GmC/switched-capacitor fourth-order (two-stage, 4-bit) cascade ΣΔ modulator is discussed to illustrate the potential benefits of the presented approach |
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