Logic decomposition of speed-independent circuits
Logic decomposition is a well-known problem in logic synthesis, but it poses new challenges when targeted to speed-independent circuits. The decomposition of a gate into smaller gates must preserve not only the functional correctness of a circuit but also speed independence, i.e., hazard freedom und...
| Autores: | , , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 1999 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/126062 |
| Acceso en línea: | https://hdl.handle.net/2117/126062 https://dx.doi.org/10.1109/5.740027 |
| Access Level: | acceso abierto |
| Palabra clave: | Asynchronous circuits Logic circuits Logic design Hazards Logic decomposition Speed indepedence Technology mapping Circuits asíncrons Circuits lògics Estructura lògica Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
| Sumario: | Logic decomposition is a well-known problem in logic synthesis, but it poses new challenges when targeted to speed-independent circuits. The decomposition of a gate into smaller gates must preserve not only the functional correctness of a circuit but also speed independence, i.e., hazard freedom under unbounded gate delays. This paper presents a new method for logic decomposition of speed-independent circuits that solves the problem in two major steps: (1) logic decomposition of complex gates and (2) insertion of new signals that preserve hazard freedom. The method is shown to be more general than previous approaches and its effectiveness is evaluated by experiments on a set of benchmarks. |
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