A new high-level synthesis methodology of cascaded continuous-time ΣΔ modulators
This brief presents an efficient method for synthesizing cascaded sigma–delta modulators implemented with continuous-time circuits. It is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as ha...
| Autores: | , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2006 |
| País: | España |
| Institución: | Consejo Superior de Investigaciones Científicas (CSIC) |
| Repositorio: | DIGITAL.CSIC. Repositorio Institucional del CSIC |
| OAI Identifier: | oai:digital.csic.es:10261/3732 |
| Acceso en línea: | http://hdl.handle.net/10261/3732 |
| Access Level: | acceso abierto |
| Palabra clave: | Analog-to-digital converters Continuous-time ΣΔ modulation |
| Sumario: | This brief presents an efficient method for synthesizing cascaded sigma–delta modulators implemented with continuous-time circuits. It is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. In addition to placing the zeroes of the loop filter in an optimum way, the proposed methodology leads to more efficient architectures in terms of circuitry complexity, power consumption and robustness with respect to circuit errors. |
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