Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+
We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25μm CMOS proc...
| Authors: | , , , , , |
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| Format: | article |
| Status: | Versión aceptada para publicación |
| Publication Date: | 2004 |
| Country: | España |
| Institution: | Universidad de Sevilla (US) |
| Repository: | idUS. Depósito de Investigación de la Universidad de Sevilla |
| OAI Identifier: | oai:idus.us.es:11441/78365 |
| Online Access: | https://hdl.handle.net/11441/78365 https://doi.org/10.1109/TCSI.2003.821308 |
| Access Level: | Open access |
| Keyword: | Analog-to-digital converters ADSL ΣΔ modulation Switched-capacitor circuits |
| Summary: | We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25μm CMOS process with metal–insulator–metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within +/-0.85 and +/-0.80 LSB, respectively. The ΣΔ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the ΣΔ modulator. |
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