Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel Application

Producción Científica

Detalles Bibliográficos
Autores: De Castro, Manuel, Osorio, Roberto R., Andújar, Francisco J., Carratalá-Sáez, Rocío, Torres, Yuri, Llanos, Diego R.
Tipo de recurso: artículo
Estado:Versión publicada
Fecha de publicación:2025
País:España
Institución:Universidad de Valladolid
Repositorio:UVaDOC. Repositorio Documental de la Universidad de Valladolid
OAI Identifier:oai:uvadoc.uva.es:10324/75870
Acceso en línea:https://doi.org/10.1109/ACCESS.2025.3551428
https://uvadoc.uva.es/handle/10324/75870
Access Level:acceso abierto
Palabra clave:Informática
Data Parallelism, FPGA, HLS, OpenCL, Portability, SYCL
1203 Ciencia de Los Ordenadores
3304 Tecnología de Los Ordenadores
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spelling Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel ApplicationDe Castro, ManuelOsorio, Roberto R.Andújar, Francisco J.Carratalá-Sáez, RocíoTorres, YuriLlanos, Diego R.InformáticaData Parallelism, FPGA, HLS, OpenCL, Portability, SYCL1203 Ciencia de Los Ordenadores3304 Tecnología de Los OrdenadoresProducción CientíficaWith the growing popularity of FPGA-based accelerators in HPC applications, new challenges have emerged, particularly in terms of programming and portability. This paper provides an overview of the current state of FPGA tools and their limitations. This study evaluates the performance and portability of two frameworks, SYCL and OpenCL, for developing HPC FPGA solutions. The case of porting a highly-parallel application to FPGAs is studied. First, naïve, low-development-effort implementations are presented using both ND-range and single-task types of kernels, and their performance is evaluated. Subsequently, an optimized FPGA-centric approach is presented and assessed using metrics from the compilation framework. Finally, the different approaches presented are implemented using OpenCL and SYCL and their performance is evaluated. Results reveal that ND-range kernels offer high portability for highly parallel applications, while single-task codes exhibit significantly lower portability. Additionally, SYCL struggles to generate efficient hardware architectures for this kind of application when described as single-task codes, although its performance when following the ND-range approach is surprisingly high.This work was supported in part by: The Spanish Ministerio de Ciencia e Innovación and by the European Regional Development Fund (ERDF) program of the European Union, under Grant PID2022-142292NB-I00 (NATASHA Project); and in part by the Junta de Castilla y León - FEDER Grants, under Grant VA226P20 (PROPHET-2 Project), Junta de Castilla y León, Spain. This work was also supported in part by grant TED2021–130367B–I00, funded by MCIN/AEI/10.13039/ 501100011033 and by “European UnionNextGenerationEU/PRTR”, and by grant PID2022-136435NB-I00, funded by MCIN/AEI/ 10.13039/501100011033 and by “ERDF A way of making Europe”, EU. Manuel de Castro has been supported by Spanish Ministerio de Ciencia, Innovación y Universidades, through “Ayudas para la Formación de Profesorado Universitario FPU 2022”.IEEE2025info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionapplication/pdfhttps://doi.org/10.1109/ACCESS.2025.3551428https://uvadoc.uva.es/handle/10324/75870reponame:UVaDOC. Repositorio Documental de la Universidad de Valladolidinstname:Universidad de ValladolidIngléshttps://ieeexplore.ieee.org/abstract/document/10926827info:eu-repo/semantics/openAccessoai:uvadoc.uva.es:10324/758702026-06-13T12:44:47Z
dc.title.none.fl_str_mv Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel Application
title Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel Application
spellingShingle Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel Application
De Castro, Manuel
Informática
Data Parallelism, FPGA, HLS, OpenCL, Portability, SYCL
1203 Ciencia de Los Ordenadores
3304 Tecnología de Los Ordenadores
title_short Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel Application
title_full Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel Application
title_fullStr Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel Application
title_full_unstemmed Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel Application
title_sort Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel Application
dc.creator.none.fl_str_mv De Castro, Manuel
Osorio, Roberto R.
Andújar, Francisco J.
Carratalá-Sáez, Rocío
Torres, Yuri
Llanos, Diego R.
author De Castro, Manuel
author_facet De Castro, Manuel
Osorio, Roberto R.
Andújar, Francisco J.
Carratalá-Sáez, Rocío
Torres, Yuri
Llanos, Diego R.
author_role author
author2 Osorio, Roberto R.
Andújar, Francisco J.
Carratalá-Sáez, Rocío
Torres, Yuri
Llanos, Diego R.
author2_role author
author
author
author
author
dc.subject.none.fl_str_mv Informática
Data Parallelism, FPGA, HLS, OpenCL, Portability, SYCL
1203 Ciencia de Los Ordenadores
3304 Tecnología de Los Ordenadores
topic Informática
Data Parallelism, FPGA, HLS, OpenCL, Portability, SYCL
1203 Ciencia de Los Ordenadores
3304 Tecnología de Los Ordenadores
description Producción Científica
publishDate 2025
dc.date.none.fl_str_mv 2025
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv https://doi.org/10.1109/ACCESS.2025.3551428
https://uvadoc.uva.es/handle/10324/75870
url https://doi.org/10.1109/ACCESS.2025.3551428
https://uvadoc.uva.es/handle/10324/75870
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv https://ieeexplore.ieee.org/abstract/document/10926827
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv IEEE
publisher.none.fl_str_mv IEEE
dc.source.none.fl_str_mv reponame:UVaDOC. Repositorio Documental de la Universidad de Valladolid
instname:Universidad de Valladolid
instname_str Universidad de Valladolid
reponame_str UVaDOC. Repositorio Documental de la Universidad de Valladolid
collection UVaDOC. Repositorio Documental de la Universidad de Valladolid
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,812429

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