Integration of Hardware Acceleration Techniques in a Real-Time Framework Using FPGA Devices

Bibliographic Details
Authors:	González Brito, César\|\|\|0000-0001-9333-906X, Ruiz González, Mariano\|\|\|0000-0002-1337-0110, Nieto Valhondo, Julián\|\|\|0000-0003-3315-7445, Carpeño Ruiz, Antonio\|\|\|0000-0001-6824-0455, Piñas Higueruela, Alejandro\|\|\|0009-0003-2903-8563, Costa Pérez, Victor\|\|\|0000-0003-2994-8420, Barrera López de Turiso, Eduardo\|\|\|0000-0001-7197-8821, Arranz Ara, German\|\|\|0009-0000-6546-6838, Lee, Woongryol, Tak, Taehyun\|\|\|0000-0003-3800-2995, Zagar, Anze\|\|\|0009-0009-2697-6013
Format:	article
Publication Date:	2025
Country:	España
Institution:	Universidad Politécnica de Madrid
Repository:	Archivo Digital UPM
OAI Identifier:	oai:oa.upm.es:89070
Online Access:	https://oa.upm.es/89070/
Access Level:	Open access
Keyword:	CODAC Core System (CCS) fieldprogrammable gate array (FPGA) hardware acceleration techniques high-level Synthesis (HLS) open computing language (OpenCL) real-time framework (RTF)

Description
Description not available.