Dual-Inductive and Programmable Switching: A New Paradigm in Ionic Interface-Controlled Perovskite Memory
[EN] While halide perovskite (HP) memristors exhibit significant potential for artificial neural networks, their reliance on stochastic filamentary switching severely compromises operational stability. Here, we demonstrate a fully programmable, forming-free HP memristor that overcomes this intrinsic...
| Autores: | , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2026 |
| País: | España |
| Institución: | Universitat Politècnica de València (UPV) |
| Repositorio: | RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia |
| Idioma: | inglés |
| OAI Identifier: | oai:dnet:riunet______::a1af346eb73ee2273d9e9f0e0c870cbe |
| Acceso en línea: | https://riunet.upv.es/handle/10251/235934 |
| Access Level: | acceso abierto |
| Palabra clave: | Dual inductive switching Halide perovskites Interface engineering Ion migration Perovskite memory Resistive switching |
| Sumario: | [EN] While halide perovskite (HP) memristors exhibit significant potential for artificial neural networks, their reliance on stochastic filamentary switching severely compromises operational stability. Here, we demonstrate a fully programmable, forming-free HP memristor that overcomes this intrinsic stochasticity through precise ionic interface engineering. By employing 1,4-butanediammonium iodide (BDAI2) as an ion-modulating layer, we construct a structurally rigid, cross-linked interfacial network strongly anchored to the 3D HP surface, forming the grain boundaries-modulated barrier switching. The robust ion-blocking barrier fundamentally suppresses random filamentary growth. Resistive switching (RS) is instead governed by dynamic interfacial barrier modulation, driven by the asymmetric accumulation of mobile ions that electrostatically modulates charge injection. Crucially, this stable non-filamentary mechanism enables highly reproducible, bidirectional dual-inductive responses, and distinct non-zero crossing behaviors. For the first time in an operational HP memristor, we successfully achieved these combined dynamic features. We precisely control programmable multi-level states governed by compliance current and operation velocity. This defect-engineered, interface-driven approach establishes a highly reliable and dynamically controllable paradigm for advanced neuromorphic computing and analog memory architectures. |
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