A 12-Bit Low-Input Capacitance SAR ADC With a Rail-to-Rail Comparator
The input capacitance of the SAR ADC is considered a drawback in many applications. In this paper, a 12-bit low-power SAR ADC with low-input capacitance is proposed. The ADC is based on a separated DAC and sample-and-hold blocks (SB) structure. The SB structure suffers from variation in the input co...
| Autores: | , , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2023 |
| País: | España |
| Institución: | Universidad de Sevilla (US) |
| Repositorio: | idUS. Depósito de Investigación de la Universidad de Sevilla |
| OAI Identifier: | oai:idus.us.es:11441/160326 |
| Acceso en línea: | https://hdl.handle.net/11441/160326 https://doi.org/10.1109/ACCESS.2023.3287652 |
| Access Level: | acceso abierto |
| Palabra clave: | Successive approximation register (SAR) Time-domain offset cancellation Kickback noise reduction Rail-to-rail Bootstrap switch |
| Sumario: | The input capacitance of the SAR ADC is considered a drawback in many applications. In this paper, a 12-bit low-power SAR ADC with low-input capacitance is proposed. The ADC is based on a separated DAC and sample-and-hold blocks (SB) structure. The SB structure suffers from variation in the input common-mode voltage of the comparator, leading to nonlinear input-referred offset and kickback noise. Here, a closed-loop low-power rail-to-rail offset cancellation technique for the comparator, based on body voltage tuning, is proposed. In order to stabilize the closed loop structure, the open loop gain is controlled by adapting the gain of the preamplifier. Using this structure, the rail-to-rail offset is kept lower than 110 μV and the overall power of the comparator is 1 pJ/Conv. Complementary-clocked dynamic branches are exploited at the input of the comparator to decrease the common-mode dependent kickback noise error to less than 1 LSB. The bootstrapped switch’s controlling signal is also modified to achieve less than 1 LSB error and 18.9% lower power consumption. The proposed ADC is designed in standard 180 nm CMOS technology with a 1.8 V supply voltage and the input capacitance is reduced to 2 pF, which leads to power consumption of 41 nW in the input voltage supply. Electrical simulations including PVT, Monte-Carlo, and post-layout parasitic extraction were conducted to ensure the effectiveness of the approach. The ADC features an ENOB of 11.1-bit and a sampling rate of 1 MHz with a power consumption of 117.9 μW including the input power supply which are competitive with the state-of-the-art, and demonstrate the virtue of the proposed approach. |
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