Trivium hardware implementations for power reduction

This paper describes the use of parallelization techniques to reduce dynamic power consumption in hardware implementations of the Trivium stream cipher. Trivium is a synchronous stream cipher based on a combination of three non-linear feedback shift registers. In 2008, it was chosen as a finalist fo...

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Detalhes bibliográficos
Autores: Mora Gutiérrez, José Miguel, Jiménez Fernández, Carlos Jesús, Valencia Barrero, Manuel
Tipo de documento: artigo
Estado:Versión enviada para evaluación y publicación
Data de publicação:2017
País:España
Recursos:Universidad de Sevilla (US)
Repositório:idUS. Depósito de Investigación de la Universidad de Sevilla
OAI Identifier:oai:idus.us.es:11441/106054
Acesso em linha:https://hdl.handle.net/11441/106054
https://doi.org/10.1002/cta.2281
Access Level:Acceso aberto
Palavra-chave:Trivium
Stream Cipher
Low-power
lightweight cryptography
Hardware implementations
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spelling Trivium hardware implementations for power reductionMora Gutiérrez, José MiguelJiménez Fernández, Carlos JesúsValencia Barrero, ManuelTriviumStream CipherLow-powerlightweight cryptographyHardware implementationsThis paper describes the use of parallelization techniques to reduce dynamic power consumption in hardware implementations of the Trivium stream cipher. Trivium is a synchronous stream cipher based on a combination of three non-linear feedback shift registers. In 2008, it was chosen as a finalist for the hardware profile of the eSTREAM project. So that their power consumption values can be compared and verified, the proposed low-power Trivium designs were implemented and characterized in 350-nm standard-cell technology with both transistors and gate-level models, in order to permit both electrical and logical simulations. The results show that the two designs decreased average power consumption by between 15% and 25% with virtually no performance loss and only a slight overhead (about 5%) in area.Ministerio de Economía y Competitividad TEC2010-16870Ministerio de Economía y Competitividad TEC2013-45523-RMinisterio de Economía y Competitividad CSIC 201550E039WileyTecnología ElectrónicaMinisterio de Economía y Competitividad (MINECO). España2017info:eu-repo/semantics/articleinfo:eu-repo/semantics/submittedVersionapplication/pdfapplication/pdfhttps://hdl.handle.net/11441/106054https://doi.org/10.1002/cta.2281reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésInternational Journal of Circuit Theory and Applications, 45 (2), 188-198.TEC2010-16870TEC2013-45523-RCSIC 201550E039https://onlinelibrary.wiley.com/doi/full/10.1002/cta.2281info:eu-repo/semantics/openAccessoai:idus.us.es:11441/1060542026-06-17T12:51:07Z
dc.title.none.fl_str_mv Trivium hardware implementations for power reduction
title Trivium hardware implementations for power reduction
spellingShingle Trivium hardware implementations for power reduction
Mora Gutiérrez, José Miguel
Trivium
Stream Cipher
Low-power
lightweight cryptography
Hardware implementations
title_short Trivium hardware implementations for power reduction
title_full Trivium hardware implementations for power reduction
title_fullStr Trivium hardware implementations for power reduction
title_full_unstemmed Trivium hardware implementations for power reduction
title_sort Trivium hardware implementations for power reduction
dc.creator.none.fl_str_mv Mora Gutiérrez, José Miguel
Jiménez Fernández, Carlos Jesús
Valencia Barrero, Manuel
author Mora Gutiérrez, José Miguel
author_facet Mora Gutiérrez, José Miguel
Jiménez Fernández, Carlos Jesús
Valencia Barrero, Manuel
author_role author
author2 Jiménez Fernández, Carlos Jesús
Valencia Barrero, Manuel
author2_role author
author
dc.contributor.none.fl_str_mv Tecnología Electrónica
Ministerio de Economía y Competitividad (MINECO). España
dc.subject.none.fl_str_mv Trivium
Stream Cipher
Low-power
lightweight cryptography
Hardware implementations
topic Trivium
Stream Cipher
Low-power
lightweight cryptography
Hardware implementations
description This paper describes the use of parallelization techniques to reduce dynamic power consumption in hardware implementations of the Trivium stream cipher. Trivium is a synchronous stream cipher based on a combination of three non-linear feedback shift registers. In 2008, it was chosen as a finalist for the hardware profile of the eSTREAM project. So that their power consumption values can be compared and verified, the proposed low-power Trivium designs were implemented and characterized in 350-nm standard-cell technology with both transistors and gate-level models, in order to permit both electrical and logical simulations. The results show that the two designs decreased average power consumption by between 15% and 25% with virtually no performance loss and only a slight overhead (about 5%) in area.
publishDate 2017
dc.date.none.fl_str_mv 2017
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/submittedVersion
format article
status_str submittedVersion
dc.identifier.none.fl_str_mv https://hdl.handle.net/11441/106054
https://doi.org/10.1002/cta.2281
url https://hdl.handle.net/11441/106054
https://doi.org/10.1002/cta.2281
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv International Journal of Circuit Theory and Applications, 45 (2), 188-198.
TEC2010-16870
TEC2013-45523-R
CSIC 201550E039
https://onlinelibrary.wiley.com/doi/full/10.1002/cta.2281
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
application/pdf
dc.publisher.none.fl_str_mv Wiley
publisher.none.fl_str_mv Wiley
dc.source.none.fl_str_mv reponame:idUS. Depósito de Investigación de la Universidad de Sevilla
instname:Universidad de Sevilla (US)
instname_str Universidad de Sevilla (US)
reponame_str idUS. Depósito de Investigación de la Universidad de Sevilla
collection idUS. Depósito de Investigación de la Universidad de Sevilla
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,198674

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