ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium
We are presenting the experimental measurements of the power consumption and the maximum frequency in an ASIC prototype of 12 versions of the Trivium cipher: one standard version and two low power versions (FPLP and MPLP) with four different radix (radix-1, radix-2, radix-8 and radix-16). It is also...
| Autores: | , , |
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| Formato: | artículo |
| Estado: | Versión enviada para evaluación y publicación |
| Fecha de publicación: | 2020 |
| País: | España |
| Recursos: | Universidad de Sevilla (US) |
| Repositorio: | idUS. Depósito de Investigación de la Universidad de Sevilla |
| OAI Identifier: | oai:idus.us.es:11441/106025 |
| Acesso em linha: | https://hdl.handle.net/11441/106025 https://doi.org/10.1109/TCSII.2020.2969242 |
| Access Level: | acceso abierto |
| Palavra-chave: | ASIC implementation IoT hardware lightweight cryptography Low-power Trivium |
| Resumo: | We are presenting the experimental measurements of the power consumption and the maximum frequency in an ASIC prototype of 12 versions of the Trivium cipher: one standard version and two low power versions (FPLP and MPLP) with four different radix (radix-1, radix-2, radix-8 and radix-16). It is also described the mechanism for measuring power consumption in each Trivium implemented in the ASIC prototype. The clock tree of the ciphers has been designed in such a way that the clock signal of each Trivium can be cut independently. The experimental setup uses the Agilent 93000 testing system. The results show that the higher radix versions have a lower operating frequency and that the lower radix low-power versions have a very high power reduction. However, the Trivium radix-16 versions generate 16 bit/clock cycle so the measurements conclude that the MPLP version is the one with the lowest power consumption per bit (0.69 pJ/bit at 50 MHz). |
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