Design of a 1-V 90-nm CMOS adaptive LNA for multi-standard wireless receivers

[EN]: This paper presents the design of a reconfigurable Low-Noise Amplifier (LNA) for the next generation of wireless hand-held devices. The circuit, based on a lumped-approach design and implemented in a 90nm standard RF CMOS technology, consists of a two-stage topology that combines inductive-sou...

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Detalles Bibliográficos
Autores: Becerra-Alvarez, Edwin C., Sandoval-Ibarra, F., Rosa, José M. de la
Tipo de recurso: artículo
Fecha de publicación:2008
País:España
Institución:Consejo Superior de Investigaciones Científicas (CSIC)
Repositorio:DIGITAL.CSIC. Repositorio Institucional del CSIC
OAI Identifier:oai:digital.csic.es:10261/86365
Acceso en línea:http://hdl.handle.net/10261/86365
Access Level:acceso abierto
Descripción
Sumario:[EN]: This paper presents the design of a reconfigurable Low-Noise Amplifier (LNA) for the next generation of wireless hand-held devices. The circuit, based on a lumped-approach design and implemented in a 90nm standard RF CMOS technology, consists of a two-stage topology that combines inductive-source degeneration with MOS-varactor based tuning networks and programmable bias currents, in order to adapt its performance to different standard specifications with reduced number of inductors and minimum power dissipation. As an application, the LNA is designed to cope with the requirements of GSM (PCS1900), WCDMA, Bluetooth and WLAN (IEEE 802.11b-g). Simulation results, including technology parasitics, demonstrate correct operation of the LNA for these standards, featuring NF<1.77dB, S21 >16dB, S11 <-5.5dB, S22 <-5.5 dB and IIP3>-3.3 dBm over the 1.85-2.48 GHz band, with an adaptive power consumption between 25.3 mW and 53.3mW. The layout of the LNA occupies an area of 1.18×1.18 μm2.