Hardware-Assisted Thread and Data Mapping in Hierarchical Multicore Architectures
The performance and energy efficiency of modern architectures depend on memory locality, which can be improved by thread and data mappings considering the memory access behavior of parallel applications. In this article, we propose intense pages mapping, a mechanism that analyzes the memory access b...
| Autores: | , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2016 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/113312 |
| Acceso en línea: | https://hdl.handle.net/2117/113312 https://dx.doi.org/10.1145/2975587 |
| Access Level: | acceso abierto |
| Palabra clave: | High performance computing Data Mapping Supercomputadors Àrees temàtiques de la UPC::Informàtica |
| Sumario: | The performance and energy efficiency of modern architectures depend on memory locality, which can be improved by thread and data mappings considering the memory access behavior of parallel applications. In this article, we propose intense pages mapping, a mechanism that analyzes the memory access behavior using information about the time the entry of each page resides in the translation lookaside buffer. It provides accurate information with a very low overhead. We present experimental results with simulation and real machines, with average performance improvements of 13.7% and energy savings of 4.4%, which come from reductions in cache misses and interconnection traffic. |
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