Hardware-assisted thread and data mapping in hierarchical multi-core architectures
The performance and energy efficiency of modern architectures depend on memory locality, which can be improved by thread and data mappings considering the memory access behavior of parallel applications. In this paper, we propose IPM, a mechanism that analyzes the memory access behavior using inform...
| Autores: | , , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2016 |
| País: | Brasil |
| Institución: | Universidade Federal do Rio Grande do Sul (UFRGS) |
| Repositorio: | Repositório Institucional da UFRGS |
| Idioma: | inglés |
| OAI Identifier: | oai:www.lume.ufrgs.br:10183/172363 |
| Acceso en línea: | http://hdl.handle.net/10183/172363 |
| Access Level: | acceso abierto |
| Palabra clave: | Memoria : Computadores |
| Sumario: | The performance and energy efficiency of modern architectures depend on memory locality, which can be improved by thread and data mappings considering the memory access behavior of parallel applications. In this paper, we propose IPM, a mechanism that analyzes the memory access behavior using information about the time the entry of each page resides in the Translation Lookaside Buffer (TLB). It provides very accurate information with a very low overhead. We present experimental results with simulation and real machines, with average performance improvements of 13.7% and energy savings of 4.4%, which come from reductions in cache misses and interconnection traffic. |
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