Logic Neural Networks for Efficient FPGA Implementation
Logic Neural Networks (LNNs) represent a new paradigm for implementing neural networks in hardware devices such as Field-Programmable Gate Arrays (FPGAs). These network architectures exhibit unique attributes that can leverage the inherent parallelism of FPGAs, enabling the development of networks c...
| Autores: | , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2024 |
| País: | España |
| Institución: | Universidad Rey Juan Carlos |
| Repositorio: | BURJC-Digital. Repositorio Institucional de la Universidad Rey Juan Carlos |
| OAI Identifier: | oai:burjcdigital.urjc.es:10115/41542 |
| Acceso en línea: | https://hdl.handle.net/10115/41542 |
| Access Level: | acceso abierto |
| Palabra clave: | Logic gates Biological neural networks Training Neurons Logic Field programmable gate arrays Hardware Logic functions Accuracy Network architecture |
| Sumario: | Logic Neural Networks (LNNs) represent a new paradigm for implementing neural networks in hardware devices such as Field-Programmable Gate Arrays (FPGAs). These network architectures exhibit unique attributes that can leverage the inherent parallelism of FPGAs, enabling the development of networks characterized by low power consumption and fast inference capabilities. Despite their potential advantages, the relative novelty of LNNs poses a challenge, as there are currently no established guidelines for defining their architectures. In this paper, we present a comprehensive study of LNNs, aiming to address the existing gap in understanding and guide decision-making during the design phase. Through systematic experimentation and analysis, we explore various aspects of logic networks, including their impact on inference time, power consumption, and overall simplicity. The findings derived from these experiments provide valuable insights for the creation of improved networks, thereby paving the way for further advancements in this field |
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