Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform

This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to su...

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Authors: Majoral M., Arribas J., Fernández-Prades C.
Format: article
Status:Published version
Publication Date:2024
Country:España
Institution:Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)
Repository:r-CTTC. Repositorio Institucional Producción Científica del Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)
OAI Identifier:oai:cttc.fundanetsuite.com:p8382
Online Access:https://cttc.fundanetsuite.com/Publicaciones/ProdCientif/PublicacionFrw.aspx?id=8382
https://www.scopus.com/inward/record.uri?eid=2-s2.0-85187536032&doi=10.3390%2fs24051416&partnerID=40&md5=0e3074fa5956cda6033fd9b645743331
Access Level:Open access
Keyword:Application specific integrated circuits
Field programmable gate arrays (FPGA)
General purpose computers
Global positioning system
Integrated circuit design
Logic gates
Programmable logic controllers
Radio navigation
Radio receivers
Satellites
Signal processing
Software radio
Field programmables
Global Navigation Satellite Systems
High sensitivity
High-sensitivity global navigation satellite system receiver
Programmable gate array
Software-defined radios
System-on-chip field-programmable gate array
Systems-on-Chip
System-on-chip
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network_name_str España
repository_id_str
spelling Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array PlatformMajoral M.Arribas J.Fernández-Prades C.Application specific integrated circuitsField programmable gate arrays (FPGA)General purpose computersGlobal positioning systemIntegrated circuit designLogic gatesProgrammable logic controllersRadio navigationRadio receiversSatellitesSignal processingSoftware radioField programmablesGlobal Navigation Satellite SystemsHigh sensitivityHigh-sensitivity global navigation satellite system receiverProgrammable gate arraySoftware-defined radiosSystem-on-chip field-programmable gate arraySystems-on-ChipSystem-on-chipThis paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs. This innovative approach enhances power efficiency compared to conventional designs relying on general-purpose processors, thereby facilitating the development of embedded software-defined receivers. Within this architecture, we implemented a modular GNSS baseband processing engine, offering a versatile platform for the integration of novel algorithms. The proposed receiver undergoes testing with live signals, showcasing its capability to process GNSS signals even in challenging scenarios with a carrier-to-noise density ratio ((Formula presented.)) as low as 20 dB-Hz, while delivering navigation solutions. This work contributes to the advancement of low-cost, high-sensitivity GNSS receivers, providing a valuable tool for researchers engaged in the development, testing, and validation of experimental GNSS signal processing techniques. © 2024 by the authors.MDPI Multidisciplinary Digital Publishing Institute2024info:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionhttps://cttc.fundanetsuite.com/Publicaciones/ProdCientif/PublicacionFrw.aspx?id=8382https://www.scopus.com/inward/record.uri?eid=2-s2.0-85187536032&doi=10.3390%2fs24051416&partnerID=40&md5=0e3074fa5956cda6033fd9b645743331SENSORSISSN: 14243210ISSNe: 14248220reponame:r-CTTC. Repositorio Institucional Producción Científica del Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)instname:Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)Inglésinfo:eu-repo/semantics/openAccessoai:cttc.fundanetsuite.com:p83822026-06-17T11:44:47Z
dc.title.none.fl_str_mv Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform
title Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform
spellingShingle Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform
Majoral M.
Application specific integrated circuits
Field programmable gate arrays (FPGA)
General purpose computers
Global positioning system
Integrated circuit design
Logic gates
Programmable logic controllers
Radio navigation
Radio receivers
Satellites
Signal processing
Software radio
Field programmables
Global Navigation Satellite Systems
High sensitivity
High-sensitivity global navigation satellite system receiver
Programmable gate array
Software-defined radios
System-on-chip field-programmable gate array
Systems-on-Chip
System-on-chip
title_short Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform
title_full Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform
title_fullStr Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform
title_full_unstemmed Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform
title_sort Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform
dc.creator.none.fl_str_mv Majoral M.
Arribas J.
Fernández-Prades C.
author Majoral M.
author_facet Majoral M.
Arribas J.
Fernández-Prades C.
author_role author
author2 Arribas J.
Fernández-Prades C.
author2_role author
author
dc.subject.none.fl_str_mv Application specific integrated circuits
Field programmable gate arrays (FPGA)
General purpose computers
Global positioning system
Integrated circuit design
Logic gates
Programmable logic controllers
Radio navigation
Radio receivers
Satellites
Signal processing
Software radio
Field programmables
Global Navigation Satellite Systems
High sensitivity
High-sensitivity global navigation satellite system receiver
Programmable gate array
Software-defined radios
System-on-chip field-programmable gate array
Systems-on-Chip
System-on-chip
topic Application specific integrated circuits
Field programmable gate arrays (FPGA)
General purpose computers
Global positioning system
Integrated circuit design
Logic gates
Programmable logic controllers
Radio navigation
Radio receivers
Satellites
Signal processing
Software radio
Field programmables
Global Navigation Satellite Systems
High sensitivity
High-sensitivity global navigation satellite system receiver
Programmable gate array
Software-defined radios
System-on-chip field-programmable gate array
Systems-on-Chip
System-on-chip
description This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs. This innovative approach enhances power efficiency compared to conventional designs relying on general-purpose processors, thereby facilitating the development of embedded software-defined receivers. Within this architecture, we implemented a modular GNSS baseband processing engine, offering a versatile platform for the integration of novel algorithms. The proposed receiver undergoes testing with live signals, showcasing its capability to process GNSS signals even in challenging scenarios with a carrier-to-noise density ratio ((Formula presented.)) as low as 20 dB-Hz, while delivering navigation solutions. This work contributes to the advancement of low-cost, high-sensitivity GNSS receivers, providing a valuable tool for researchers engaged in the development, testing, and validation of experimental GNSS signal processing techniques. © 2024 by the authors.
publishDate 2024
dc.date.none.fl_str_mv 2024
dc.type.none.fl_str_mv info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
format article
status_str publishedVersion
dc.identifier.none.fl_str_mv https://cttc.fundanetsuite.com/Publicaciones/ProdCientif/PublicacionFrw.aspx?id=8382
https://www.scopus.com/inward/record.uri?eid=2-s2.0-85187536032&doi=10.3390%2fs24051416&partnerID=40&md5=0e3074fa5956cda6033fd9b645743331
url https://cttc.fundanetsuite.com/Publicaciones/ProdCientif/PublicacionFrw.aspx?id=8382
https://www.scopus.com/inward/record.uri?eid=2-s2.0-85187536032&doi=10.3390%2fs24051416&partnerID=40&md5=0e3074fa5956cda6033fd9b645743331
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.publisher.none.fl_str_mv MDPI Multidisciplinary Digital Publishing Institute
publisher.none.fl_str_mv MDPI Multidisciplinary Digital Publishing Institute
dc.source.none.fl_str_mv SENSORS
ISSN: 14243210
ISSNe: 14248220
reponame:r-CTTC. Repositorio Institucional Producción Científica del Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)
instname:Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)
instname_str Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)
reponame_str r-CTTC. Repositorio Institucional Producción Científica del Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)
collection r-CTTC. Repositorio Institucional Producción Científica del Centre Tecnològic de Telecomunicacions de Catalunya (CTTC)
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,811543

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