Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform
This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to su...
| Autores: | , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2024 |
| País: | España |
| Institución: | Centre Tecnològic de Telecomunicacions de Catalunya (CTTC) |
| Repositorio: | r-CTTC. Repositorio Institucional Producción Científica del Centre Tecnològic de Telecomunicacions de Catalunya (CTTC) |
| OAI Identifier: | oai:cttc.fundanetsuite.com:p8382 |
| Acceso en línea: | https://cttc.fundanetsuite.com/Publicaciones/ProdCientif/PublicacionFrw.aspx?id=8382 https://www.scopus.com/inward/record.uri?eid=2-s2.0-85187536032&doi=10.3390%2fs24051416&partnerID=40&md5=0e3074fa5956cda6033fd9b645743331 |
| Access Level: | acceso abierto |
| Palabra clave: | Application specific integrated circuits Field programmable gate arrays (FPGA) General purpose computers Global positioning system Integrated circuit design Logic gates Programmable logic controllers Radio navigation Radio receivers Satellites Signal processing Software radio Field programmables Global Navigation Satellite Systems High sensitivity High-sensitivity global navigation satellite system receiver Programmable gate array Software-defined radios System-on-chip field-programmable gate array Systems-on-Chip System-on-chip |
| Sumario: | This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs. This innovative approach enhances power efficiency compared to conventional designs relying on general-purpose processors, thereby facilitating the development of embedded software-defined receivers. Within this architecture, we implemented a modular GNSS baseband processing engine, offering a versatile platform for the integration of novel algorithms. The proposed receiver undergoes testing with live signals, showcasing its capability to process GNSS signals even in challenging scenarios with a carrier-to-noise density ratio ((Formula presented.)) as low as 20 dB-Hz, while delivering navigation solutions. This work contributes to the advancement of low-cost, high-sensitivity GNSS receivers, providing a valuable tool for researchers engaged in the development, testing, and validation of experimental GNSS signal processing techniques. © 2024 by the authors. |
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