A Robust Three-Phase Pre-Filtered Phase Locked-Loop for the Sub-Cycle Estimation of Fundamental Parameters
This article shows a proposal for a nonadaptive prefilter based three-phase type-I synchronous reference frame-based phase locked-loop (PLL) algorithm. This solution is simpler than the widely accepted type-II PLL algorithms, which require a great deal of effort as regards tuning the proportional-in...
| Autores: | , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2021 |
| País: | España |
| Institución: | Universidad de Castilla-La Mancha |
| Repositorio: | RUIdeRA. Repositorio Institucional de la UCLM |
| OAI Identifier: | oai:ruidera.uclm.es:10578/40303 |
| Acceso en línea: | https://hdl.handle.net/10578/40303 |
| Access Level: | acceso abierto |
| Palabra clave: | Delayed signal cancellation (DSC) operator moving average filter (MAF) orthogonal signal generation (OSG) phase-locked loop (PLL) three-phase grid voltage |
| Sumario: | This article shows a proposal for a nonadaptive prefilter based three-phase type-I synchronous reference frame-based phase locked-loop (PLL) algorithm. This solution is simpler than the widely accepted type-II PLL algorithms, which require a great deal of effort as regards tuning the proportional-integral gains. In the proposed approach, a type-I controller that is merely a proportional gain with a fixed magnitude is employed. Moreover, improvements are made to the implementation of the nonadaptive demodulation based prefiltering approach, which consist of moving average filters and delayed signal cancellation operators. In the event of a fault, the improved prefilter structure is still incapable of rejecting the fundamental negative sequence (FNS) component. We propose to overcome this issue by using a nonadaptive computationally simplified structure to improve the immunity to the adverse effects of FNS. It is consequently possible to avoid the dependence on the frequency feedback loop while involving a simple and fast feed-forward error compensation approach. Finally, the performance of the proposed PLL is experimentally verified using a real-time controller to demonstrate its feasibility for grid synchronization applications. |
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