Computational implementation of a tunable multicellular memory circuit for engineered eukaryotic consortia
Cells are complex machines capable of processing information by means of an entangled network of molecular interactions. A crucial component of these decision-making systems is the presence of memory and this is also a specially relevant target of engineered synthetic systems. A classic example of m...
| Autores: | , , , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2015 |
| País: | España |
| Institución: | Varias* (Consorci de Biblioteques Universitáries de Catalunya, Centre de Serveis Científics i Acadèmics de Catalunya) |
| Repositorio: | Recercat. Dipósit de la Recerca de Catalunya |
| OAI Identifier: | oai:recercat.cat:10230/25661 |
| Acceso en línea: | http://hdl.handle.net/10230/25661 http://dx.doi.org/10.3389/fphys.2015.00281 |
| Access Level: | acceso abierto |
| Palabra clave: | Molècules -- Models Computational modeling Eukaryotic memory circuits Flip-flop Multicellular circuits Synthetic biology |
| Sumario: | Cells are complex machines capable of processing information by means of an entangled network of molecular interactions. A crucial component of these decision-making systems is the presence of memory and this is also a specially relevant target of engineered synthetic systems. A classic example of memory devices is a 1-bit memory element known as the flip-flop. Such system can be in principle designed using a single-cell implementation, but a direct mapping between standard circuit design and a living circuit can be cumbersome. Here we present a novel computational implementation of a 1-bit memory device using a reliable multicellular design able to behave as a set-reset flip-flop that could be implemented in yeast cells. The dynamics of the proposed synthetic circuit is investigated with a mathematical model using biologically-meaningful parameters. The circuit is shown to behave as a flip-flop in a wide range of parameter values. The repression strength for the NOT logics is shown to be crucial to obtain a good flip-flop signal. Our model also shows that the circuit can be externally tuned to achieve different memory states and dynamics, such as persistent and transient memory. We have characterized the parameter domains for robust memory storage and retrieval as well as the corresponding time response dynamics. |
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