Low-power SiPM readout BETA ASIC for space applications

The BETA application-specific integrated circuit (ASIC) is a fully programmable chip designed to amplify, shape and digitize the signal of up to 64 Silicon photomultiplier (SiPM) channels, with a power consumption of approximately 1 mW/channel. Owing to its dual-path gain, the BETA chip is capable o...

ver descrição completa

Detalhes bibliográficos
Autores: Siddharudh Sanmukh, Anand, Gómez Fernández, Sergio|||0000-0002-3064-9834, Comerma Montells, Albert|||0000-0002-8980-6048, Mauricio Ferré, Joan, Manera Escalero, Rafel, Sanuy Charles, Andreu, Guberman, Daniel|||0000-0002-9636-1825, Català Mejias, Roger, Espinya Rojas, Albert, Orta Terré, Marina, Torre Pérez, Oscar de la, Gascón Fora, David
Formato: artículo
Fecha de publicación:2024
País:España
Recursos:Universitat Politècnica de Catalunya (UPC)
Repositorio:UPCommons. Portal del coneixement obert de la UPC
Idioma:inglés
OAI Identifier:oai:upcommons.upc.edu:2117/408197
Acesso em linha:https://hdl.handle.net/2117/408197
https://dx.doi.org/10.1007/s41365-024-01419-z
Access Level:acceso abierto
Palavra-chave:Analog integrated circuits
Circuits integrats analògics
Detectors
Àrees temàtiques de la UPC::Enginyeria electrònica::Instrumentació i mesura::Sensors i actuadors
Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal
Descrição
Resumo:The BETA application-specific integrated circuit (ASIC) is a fully programmable chip designed to amplify, shape and digitize the signal of up to 64 Silicon photomultiplier (SiPM) channels, with a power consumption of approximately 1 mW/channel. Owing to its dual-path gain, the BETA chip is capable of resolving single photoelectrons (phes) with a signal-to-noise ratio (SNR) >5 while simultaneously achieving a dynamic range of 4000 phes. Thus, BETA can provide a cost-effective solution for the readout of SiPMs in space missions and other applications with a maximum rate below 10 kHz. In this study, we describe the key characteristics of the BETA ASIC and present an evaluation of the performance of its 16-channel version, which is implemented using 130 nm technology. The ASIC also contains two discriminators that can provide trigger signals with a time jitter down to 400 ps FWHM for 10 phes. The linearity error of the charge gain measurement was less than 2% for a dynamic range as large as 15 bits.