Low-power SiPM readout BETA ASIC for space applications
The BETA application-specific integrated circuit (ASIC) is a fully programmable chip designed to amplify, shape and digitize the signal of up to 64 Silicon photomultiplier (SiPM) channels, with a power consumption of approximately $$\sim$$1 mW/channel. Owing to its dual-path gain, the BETA chip is c...
| Autores: | , , , , , , , , , , , |
|---|---|
| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2024 |
| País: | España |
| Institución: | Varias* (Consorci de Biblioteques Universitáries de Catalunya, Centre de Serveis Científics i Acadèmics de Catalunya) |
| Repositorio: | Recercat. Dipósit de la Recerca de Catalunya |
| OAI Identifier: | oai:recercat.cat:2445/216277 |
| Acceso en línea: | https://hdl.handle.net/2445/216277 |
| Access Level: | acceso abierto |
| Palabra clave: | Circuits integrats Silici Disseny de circuits electrònics Integrated circuits Silicon Electronic circuit design |
| Sumario: | The BETA application-specific integrated circuit (ASIC) is a fully programmable chip designed to amplify, shape and digitize the signal of up to 64 Silicon photomultiplier (SiPM) channels, with a power consumption of approximately $$\sim$$1 mW/channel. Owing to its dual-path gain, the BETA chip is capable of resolving single photoelectrons (phes) with a signal-to-noise ratio (SNR) >5 while simultaneously achieving a dynamic range of $$\sim$$4000 phes. Thus, BETA can provide a cost-effective solution for the readout of SiPMs in space missions and other applications with a maximum rate below 10 kHz. In this study, we describe the key characteristics of the BETA ASIC and present an evaluation of the performance of its 16-channel version, which is implemented using 130 nm technology. The ASIC also contains two discriminators that can provide trigger signals with a time jitter down to 400 ps FWHM for 10 phes. The linearity error of the charge gain measurement was less than 2% for a dynamic range as large as 15 bits. |
|---|