Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations
A lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables the possibility to objectively compare the lithography quality of different...
| Autores: | , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2014 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/26792 |
| Acceso en línea: | https://hdl.handle.net/2117/26792 https://dx.doi.org/10.1117/1.JMM.13.3.033016 |
| Access Level: | acceso abierto |
| Palabra clave: | Nanoelectronics Lithography Design for manufacturability Lithography hotspots Yield estimation Layout design Nanoelectrònica Litografia Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
| Sumario: | A lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables the possibility to objectively compare the lithography quality of different layout design implementations. Moreover, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the litho degradation. The application of the yield model is demonstrated for different layout configurations showing that a certain degree of layout regularity improves the parametric yield and increases the number of good dies per wafer. (C) 2014 Society of Photo-Optical Instrumentation Engineers (SPIE) |
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